isla214p Intersil Corporation, isla214p Datasheet
isla214p
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isla214p Summary of contents
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... Designed with Intersil’s proprietary FemtoCharge™ technology on a standard CMOS process, the series supports sampling rates 250MSPS. The ISLA214P is part of a pin-compatible family 16-bit A/Ds with maximum sample rates ranging from 130MSPS to 500MSPS. A serial peripheral interface (SPI) port allows for extensive configurability, as well as fine control of various parameters such as gain and offset ...
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... AVSS 8 VINN 9 VINN 10 VINP 11 VINP 12 AVSS 13 AVDD 14 AVSS 15 CLKDIV 16 IPTAT 17 DNC Connect Thermal Pad to AVSS RESETN ISLA214P ISLA214P (72 LD QFN) TOP VIEW Thermal Pad Not Drawn to Scale ...
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... D4P 53 D3N 54 D3P 55 D2N 56 D2P 57 D1N 3 ISLA214P LVDS PIN FUNCTION Do Not Connect 1.8V Analog Supply Analog Ground 1.8V Output Supply Output Ground Tri-Level Power Control (Nap, Sleep modes) Common Mode Output Analog Input Negative Analog Input Positive Tri-Level Clock Divider Control Temperature Monitor (Output current proportional to absolute ...
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... LVDS Bit 1 True LVDS Bit 0 (LSB) Output Complement LVDS Bit 0 (LSB) Output True LVDS Over Range Complement, True SPI Serial Data Output SPI Chip Select (active low) SPI Clock SPI Serial Data Input/Output Analog Ground ISLA214P (72 LD QFN) TOP VIEW ...
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... OR 66 SDO 67 CSB 68 SCLK 69 SDIO Exposed Paddle AVSS 5 ISLA214P CMOS PIN FUNCTION Do Not Connect 1.8V Analog Supply Analog Ground 1.8V Output Supply Output Ground Tri-Level Power Control (Nap, Sleep modes) Common Mode Output Analog Input Negative Analog Input Positive Tri-Level Clock Divider Control ...
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... RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. For Moisture Sensitivity Level (MSL), please see device information page for ISLA214P. For more information on MSL please see techbrief TB363. 6 ...
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... Digital Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 SPI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Equivalent Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 A/D Evaluation Platform Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Split Ground and Power Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Clock Input Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Exposed Paddle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Bypass and Filtering LVDS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 LVCMOS Outputs Unused Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7 ISLA214P 8 FN7572.1 May 11, 2011 ...
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... All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, = -1dBFS ISLA214P25 MIN MAX CONDITIONS (Note 5) TYP (Note 5) 1.95 2.0 2.1 600 4.5 108 -5.0 -1.7 5.0 0.94 2.6 0.9 1.8 1.7 1.8 1.9 1.7 1.8 1.9 188 200 78.5 88 signal 40 P-P θ (°C/ Maximum Conversion Rate (per speed grade). SAMPLE ISLA214P20 ISLA214P13 MIN MAX MIN (Note 5) TYP (Note 5) (Note 5) TYP (Note 5) 1.95 2.0 2.1 1.95 2.0 600 600 4.5 4 -5.0 -1.7 5.0 -5.0 -1.7 0.94 0.94 2.6 2.6 0.9 0.9 1.8 1.8 1.7 1.8 1.9 1.7 1.8 1.7 1.8 1.9 1.7 1.8 174 ...
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... Maximum Conversion Rate (per speed grade). SAMPLE ISLA214P20 ISLA214P13 MIN MAX MIN (Note 5) TYP (Note 5) (Note 5) TYP (Note 5) 422 369 448 482 397 410 360 392 313 375 310 52 400 630 -0.99 0.25 1.4 -0.99 0.25 ± ± ...
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... Maximum Conversion Rate (per speed grade). SAMPLE ISLA214P20 ISLA214P13 MIN MAX MIN (Note 5) TYP (Note 5) (Note 5) TYP ...
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... The voltage is expressed in peak-to-peak differential swing. The peak-to-peak singled-ended swing is 1/2 of the differential swing. Timing Diagrams INP INN t A CLKN CLKP t CPD CLKOUTN CLKOUTP D[12/10/8/6/4/2/0]N D[12/10/8/6/4/2/0]P 11 ISLA214P SYMBOL CONDITIONS V ICM Ipd R Ipu V 3mA Mode T V 3mA Mode ...
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... Timing Diagrams (Continued) INP INN CLKN CLKP t CLKOUTN CLKOUTP D[13:0]N D[13:0]P INP INN t CLKN CLKP t CPD CLKOUT D[12/10/8/6/4/2/0] 12 ISLA214P t A LATENCY = L CYCLES CPD DATA DATA N-L N-L+1 FIGURE 1B. LVDS SDR FIGURE 1. LVDS TIMING DIAGRAMS A LATENCY = L CYCLES ODD EVEN ODD N-L N-L N-L+1 FIGURE 2A. CMOS DDR ...
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... Synchronous Clock Divider Reset Setup Time (with respect to the positive edge of CLKP) Synchronous Clock Divider Reset Hold Time (with respect to the positive edge of CLKP) Synchronous Clock Divider Reset Recovery Time Latency (Pipeline Delay) Overvoltage Recovery 13 ISLA214P t A LATENCY = L CYCLES t CPD ...
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... SNR @ 250MSPS SNR @ 130MSPS 60 0 100 200 300 INPUT FREQUENCY (MHz) FIGURE 3. SNR AND SFDR ISLA214P Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) SYMBOL CONDITION t Write Operation CLK t Read Operation CLK t Read or Write S t ...
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... LVDS 400 375 350 325 300 100 120 140 160 180 200 SAMPLE RATE (MSPS) FIGURE 9. POWER 3mA LVDS MODE (SDR) AND SAMPLE CMOS MODE (DDR) 15 ISLA214P -30 -40 -50 -60 -70 SNR (dBc) -80 -90 -100 -110 -20 - -75 -80 -85 -90 ...
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... CODE FIGURE 13. NOISE HISTOGRAM -1.0 dBFS IN SNR = 72.6 dBFS -20 SFDR = 78.1 dBc SINAD = 71.2 dBFS -40 -60 -80 -100 -120 FREQUENCY (MHz) FIGURE 15. SINGLE-TONE SPECTRUM @ 190MHz 16 ISLA214P 0.75 0 -20 -40 35036 -60 -80 10120 -100 590 -120 8180 8182 8184 FIGURE 14. SINGLE-TONE SPECTRUM @ 105MHz ...
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... FIGURE 17. TWO-TONE SPECTRUM (F1 = 70MHz 71MHz AT -7dBFS) Theory of Operation Functional Description The ISLA214P is based on a 14-bit, 250MSPS A/D converter core that utilizes a pipelined successive approximation architecture (see Figure 19). The input voltage is captured by a Sample-Hold Amplifier (SHA) and converted to a unit of charge. Proprietary charge-domain techniques are used to successively compare the input to a series of reference charges ...
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... STAGE 2.5-BIT 1.5-BIT/ STAGE FLASH FLASH FIGURE 19. A/D CORE BLOCK DIAGRAM The performance of the ISLA214P changes with variations in temperature, supply voltage or sample rate. The extent of these changes may necessitate recalibration, depending on system CALIBRATION performance requirements. Best performance will be achieved TIME by recalibrating the A/D under the environmental conditions at which it will operate. A supply voltage variation of < ...
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... DEVICE CALIBRATED AT +25° -2dBFS ANALOG INPUT -1dBFS ANALOG INPUT TEMPERATURE (°C) FIGURE 25. TYPICAL SNR PERFORMANCE vs TEMPERATURE, DEVICE CALIBRATED AT +85° ISLA214P -40 -25 -20 FIGURE 22. TYPICAL SFDR PERFORMANCE vs TEMPERATURE, = 105MHz ...
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... VCM. The value of the shunt resistor should be determined based on the desired load impedance. The differential input resistance of the ISLA214P is 600Ω. The SHA design uses a switched capacitor input stage (see Figure 43), which creates current spikes when the sampling capacitance is reconnected to the input voltage ...
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... An external resistor creates the bias for the LVDS drivers. A 10kΩ, 1% resistor must be connected from the RLVDS pin to OVSS. Power Dissipation The power dissipated by the ISLA214P is primarily dependent on the sample rate and the output modes: LVDS vs CMOS and DDR vs SDR. There is a static bias in the analog supply, while the remaining power dissipation is linearly related to the sample rate ...
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... GRAY CODE FIGURE 33. BINARY TO GRAY CODE CONVERSION 22 ISLA214P Converting back to offset binary from Gray code must be done recursively, using the result of each bit for the next lower bit as shown in Figure 34. GRAY CODE • • • • • • • • ...
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... CLKDIVRSTN is not shown, but must be driven, and is the compliment of CLKDIVRSTP. 15. Either Output Clock Phase (phase 1 or phase 2 ) equally likely prior to synchronization. CSB SCLK SDIO R CSB SCLK SDIO ISLA214P s1 L+t d (Note 13 RSTH (Note 14) t RSTS ADC1 OUTPUT DATA s0 s1 ADC2 OUTPUT DATA ...
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... W0 A12 t DSW t S CSB t DHW SCLK SDIO W1 W0 A12 R/W SDO CSB SCLK SDIO INSTRUCTION/ADDRESS CSB SCLK SDIO INSTRUCTION/ADDRESS 24 ISLA214P t t CLK HI t DHW t LO A11 A10 SPI WRITE FIGURE 38. SPI WRITE t t CLK HI t DVR t LO WRITING A READ COMMAND ...
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... The SPI port operates in a half duplex master/slave configuration, with the ISLA214P functioning as a slave. Multiple slave devices can interface to a single master in three-wire mode only, since the SDO output of an unaddressed device is asserted in four wire mode ...
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... The default value of each register will be the result of the self-calibration after initial power-up register incremented or decremented, the user should first read the register value then write the incremented or decremented value back to the same register. 26 ISLA214P 0x22[3:0] core 0 0x26[3:0] core 1 Bit3 Bit2 Bit1 Bit0 TABLE 7 ...
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... Clock (250MHz) 2 clock_slip FIGURE 42. PHASE SLIP ADDRESS 0X72: CLOCK_DIVIDE The ISLA214P has a selectable clock divider that can be set to divide by four, two or one (no division). By default, the tri-level CLKDIV pin selects the divisor. This functionality can be overridden and controlled through the SPI, as shown in Table 9. ...
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... ADDRESS 0XCD: USER_PATT7_LSB ADDRESS 0XCE: USER_PATT7_MSB These registers define the lower and upper eight bits, respectively, of the user-defined pattern 7. 28 ISLA214P ADDRESS 0XCF: USER_PATT8_LSB ADDRESS 0XD0: USER_PATT8_MSB These registers define the lower and upper eight bits, respectively, of the user-defined pattern 8. Digital Temperature Sensor ...
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... Modes_adc1 2C-2F Reserved 33-4A Reserved 4B Temp_counter_high 4C Temp_counter_low 4D Temp_counter_control 4E-6F Reserved 70 Skew_diff 71 Phase_slip 72 Clock_divide 29 ISLA214P BIT 7 (MSB) BIT 6 BIT 5 BIT 4 SDO Active LSB First Soft Reset Reserved Burst end address [7:0] Reserved Chip ID # Chip Version # Reserved Reserved Coarse Offset Fine Offset Reserved Medium Gain Fine Gain ...
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... Use test_io = 0x80 and User Pattern 1 = 0x9999 for Checkerboard outputs in DDR mode. In SDR mode, write ‘0x41’ to test_io for Checkerboard outputs. 17. Use test_io = 0x80 and User Pattern 1 = 0xAAAA for all ones/zeroes outputs in DDR mode. In SDR mode, write ‘0x71’ to test_io for all ones/zeroes outputs 30 ISLA214P BIT 7 (MSB) BIT 6 ...
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... AVDD 75k AVDD 75k 280 INPUT 75k FIGURE 45. TRI-LEVEL DIGITAL INPUTS OVDD 2mA OR 3mA DATA DATA OVDD DATA DATA 2mA OR 3mA FIGURE 47. LVDS OUTPUTS 31 ISLA214P CLKP TO CHARGE PIPELINE E3 TO CHARGE PIPELINE CLKN E3 AVDD (20k PULL-UP ON RESETN ONLY) TO SENSE LOGIC INPUT 75k ...
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... Longer traces will increase inductance, resulting in diminished dynamic performance and accuracy. Make sure that connections to ground are direct and low impedance. Avoid forming ground loops. 32 ISLA214P AVDD + – FIGURE 49. VCM_OUT OUTPUT LVDS Outputs Output traces and connections must be designed for 50Ω (100Ω ...
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... No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see 33 ISLA214P Pipeline Delay is the number of clock cycles between the initiation of a conversion and the appearance at the output pins of the data ...
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... Tiebar shown (if present non-functional feature. 5. The configuration of the pin #1 identifier is optional, but must be 6. located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature. Package outline compliant to JESD-M0220 ISLA214P A X EXPOSED B PAD AREA 9.75 10.00 0.100 ...