isl706xrheval1z Intersil Corporation, isl706xrheval1z Datasheet - Page 2

• Manufacturer Part Number: isl706xrheval1z
• Description: Rad-hard, 5.0v/3.3v µ-processor Supervisory Circuits
• Manufacturer: Intersil Corporation

Pin Descriptions
Pin Configurations
ISL705ARH
ISL706ARH
1
2
3
4
5
6
7
8
-
-
ISL705ARH, ISL705BRH, ISL705CRH, ISL706ARH, ISL706BRH, ISL706CRH
V
GND
DD
MR
PFI
ISL705ARH, ISL706ARH
1
2
3
4
(8 LD FLATPACK)
ISL705BRH
ISL706BRH
TOP VIEW
1
2
3
4
5
6
7
8
-
-
8
7
6
5
2
ISL705CRH
ISL706CRH
WDO
RST
WDI
PFO
1
2
3
4
5
6
7
8
-
-
RST_OD
NAME
WDO
GND
V DD
WDI
PFO
RST
RST
MR
PFI
V
GND
DD
MR
PFI
ISL705BRH, ISL706BRH
Manual Reset. MR is an active-low, debounced, TTL/CMOS compatible input that may
be used to trigger a reset pulse.
Power Supply. V
This input is also monitored and used to trigger a reset pulse. Reset is guaranteed
operable after V
Ground. GND is a supply voltage return for all internal circuitry. This return establishes
the reference level for voltage detection and should be connected to signal ground.
Power Fail Input. PFI is an input to a threshold detector, which may be used to monitor
another supply voltage level. The threshold of the detector (V
ISL705ARH/BRH/CRH and 0.6V in the ISL706ARH/BRH/CRH.
Power Fail Output. PFO is an active-low, push-pull output of a threshold detector that
indicates the voltage at the PFI pin is less than V
Watchdog Input. WDI is a tri-state input that monitors microprocessor activity. If the
microprocessor does not toggle WDI within 1.6s and WDI is not tri-stated, WDO goes
low. As long as reset is asserted or WDI is tri-stated, the watchdog timer will stay cleared
and will not count. As soon as reset is released and WDI is driven high or low, the timer
will start counting. Floating WDI or connecting WDI to a high impedance tri-state buffer
disables the watchdog feature.
Reset. RST is an active-low, push-pull output that is guaranteed to be low once V
reaches 1.2V. As V
(ISL705ARH/BRH/CRH) or 3.08V (ISL706ARH/BRH/CRH) reset threshold, an internal
timer releases RST after about 200ms. RST pulses low whenever V
reset threshold. If a brownout condition occurs in the middle of a previously initiated
reset pulse, the pulse will continue for at least 140ms. On power-down, once V
below the reset threshold, RST goes low and is guaranteed low until V
1.2V.
Reset. RST is an active-high, push-pull output. RST is the inverse of RST.
Reset. RST_OD is an active-low, open-drain output that goes low when reset is asserted.
This pin may be pulled up to V
current specifications of the output. Behavior is otherwise identical to the RST pin.
Watchdog Output. WDO is an active-low, push-pull output that goes low if the
microprocessor does not toggle WDI within 1.6s and WDI is not tri-stated. WDO is
usually connected to the non-maskable interrupt input of a microprocessor. When V
drops below the reset threshold, WDO will go low whether or not the watchdog timer
has timed out. Reset is simultaneously asserted, thus preventing an interrupt. Since
floating WDI disables the internal timer, WDO goes low only when V
reset threshold, thus functioning as a low line output.
1
2
3
4
(8 LD FLATPACK)
TOP VIEW
DD
DD
DD
is a supply voltage input that provides power to all internal circuitry.
8
7
6
5
rises above 1.2V.
rises, RST stays low. When V
WDO
RST
WDI
PFO
DD
with a resistor consistent with the sink and leakage
DESCRIPTION
V
GND
DD
MR
PFI
ISL705CRH, ISL706CRH
PFI
DD
.
1
2
3
4
(8 LD FLATPACK)
rises above a 4.65V
TOP VIEW
PFI
) is 1.25V in the
DD
DD
DD
8
7
6
5
drops below the
goes below the
December 1, 2011
drops below
WDO
RST_OD
WDI
PFO
FN7662.1
DD
DD
falls
DD