isl1220 Intersil Corporation, isl1220 Datasheet
isl1220
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isl1220 Summary of contents
Page 1
... Data Sheet Low Power RTC with 8 Bytes of Battery Backed SRAM and Separate F The ISL1220 device is a low power real time clock with timing and crystal compensation, clock/calendar, power fail indicator, periodic or polled alarm, intelligent battery backup switching, battery-backed user SRAM and separate F and IRQ outputs ...
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... OR’ed with other open drain or open collector outputs. 8 SCL The Serial Clock (SCL) input is used to clock all serial data into and out of the device. 9 IRQ Interrupt Output. Open drain output, active low Power supply ISL1220 CONTROL INTERFACE LOGIC RTC DIVIDER POR FREQUENCY ALARM ...
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... Serial Interface Specifications SYMBOL PARAMETER SERIAL INTERFACE SPECS V SDA and SCL Input Buffer LOW IL Voltage 3 ISL1220 Thermal Information Pins Thermal Resistance (Typical, Note 1) OUT 10 Ld MSOP Package . . . . . . . . . . . . . . . . . . . . . . . Moisture Sensitivity (see Technical Brief TB363 Level 2 + 0.5 (V Mode) Maximum Junction Temperature (Plastic Package 150°C ...
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... These are I C specific parameters and are not directly tested, however they are used during device testing to validate device specification write to register 08h should only be done ISL1220 Over the recommended operating conditions unless otherwise specified. (Continued) TEST CONDITIONS T = 25° 1MHz, V ...
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... SDA (OUTPUT TIMING) Symbol Table WAVEFORM INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don’t Care: Changes Allowed N/A 5 ISL1220 HIGH LOW t SU:DAT t HD:DAT OUTPUTS Will be steady Will change from LOW to HIGH Will change ...
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... TEMPERATURE (°C) FIGURE TEMPERATURE DD1 2.1E-6 2.0E-6 1.9E-6 1.8E-6 1.7E-6 1.6E-6 1.5E-6 1.4E-6 1.3E-6 1.2E-6 F OUT (Hz) FIGURE DD1 OUT 6 ISL1220 Temperature is +25°C unless otherwise specified 000E+0 4.5 5.0 5.5 BAT 800.0E-9 600.0E-9 400.0E 3.3V DD 1E-6 800E-9 600E-9 400E-9 200E-9 -40 - TEMPERATURE (°C) FIGURE TEMPERATURE AT V BAT 2 ...
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... Many types of batteries can be used with Intersil RTC products. For example, 3.0V or 3.6V Lithium batteries are appropriate, and battery sizes are available that can power the ISL1220 for years. Another option is to use supplies power to the device in the event that the V pin is activated to minimize power consumption ...
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... V example, battery-backed RTCs are commonly packaged on BAT TRIP a board with a battery connected. In order to preserve battery life, the ISL1220 will not draw any power from the battery source until after the device is first powered up from the V DD battery backup mode whenever V Real Time Clock Operation 3 ...
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... The frequency output can be enabled/disabled during battery backup mode using the FOBATB bit. General Purpose User SRAM The ISL1220 provides 8 bytes of user SRAM. The SRAM will continue to operate in battery backup mode. However should be noted that the I C bus is disabled in battery backup mode ...
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... USR8 USR87 10 ISL1220 instruction latches all clock registers into a buffer update of the clock does not change the time being read. A sequential read will not result in the output of data from the memory array. At the end of a read, the master supplies a stop condition to end the operation and free the bus ...
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... Years divisible by 100 are not leap years, unless they are also divisible by 400. This means that the year 2000 is a leap year, the year 2100 is not. The ISL1220 does not correct for the leap year in the year 2100. ...
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... There is a supply current saving of DD BAT BATHYS about 600nA when using LPMODE = “1” with V 12 ISL1220 >V , then no (See Typical Performance Curves: I BAT DD LPMODE ON AND OFF.) ALARM ENABLE BIT (ALME) This bit enables/disables the alarm function. When the ALME bit is set to “ ...
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... Note that these are typical values. BATTERY MODE ATR SELECTION (BMATR <1:0>) Since the accuracy of the crystal oscillator is dependent on the V /V operation, the ISL1220 provides the capability DD BAT to adjust the capacitance between V DD device switches between power sources. ...
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... Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (See Figure 12). On power up of the ISL1220, the SDA pin is in the input mode. 2 All I ...
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... SDA line LOW to acknowledge the reception of the eight bits of data (See Figure 13). The ISL1220 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and SCL SDA START FIGURE 12. VALID DATA CHANGES, START AND STOP CONDITIONS ...
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... Identification byte with the R/W bit set to “1”. After each of the three bytes, the ISL1220 responds with an ACK. Then the ISL1220 transmits Data Bytes as long as the master responds with an ACK during the SCL cycle following the eighth bit of each byte. The master terminates the read operation (issuing a STOP condition) following the last bit of the last Data Byte (See Figure 16) ...
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... ISL1220 In addition to the analog compensation afforded by the adjustable load capacitance, a digital compensation feature is available for the ISL1220. There are 3 bits known as the Digital Trimming Register (DTR). The range provided is ±60ppm in increments of 20ppm. DTR operates by adding or skipping pulses in the clock counter very useful for ...
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... A Super Capacitor can be used as an alternative to a battery in cases where shorter backup times are required. Since the battery backup supply current required by the ISL1220 is extremely low possible to get months of backup operation using a Super Capacitor. Typical capacitor values are a few µ Farad or more depending on the application ...
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... BAT voltage from fully charged to loss of operation. Note that I is the total of the supply current of the ISL1220 (I TOT plus the leakage current of the capacitor and the diode these calculations assumed to be extremely small LKG and will be ignored ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 20 ISL1220 M10.118 (JEDEC MO-187BA) 10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE SYMBOL ...