isl33001 Intersil Corporation, isl33001 Datasheet - Page 10

• Manufacturer Part Number: isl33001
• Description: 2-wire Bus Buffer With Rise Time Accelerators And Hot Swap Capability
• Manufacturer: Intersil Corporation

For lightly loaded buses, having the accelerators active
may cause ringing or noise on the rising edge transition.
Disabling the accelerators will have the buffers continue
to perform level shifting with the V
and provide capacitance buffering.
Propagation Delays
On a low to high transition, the rising edge signal is
determined by the bus pull-up resistor, load capacitance,
and the accelerator current from the ISL33001,
ISL33002, ISL33003 buffer. Prior to the accelerators
becoming active, the buffer is connected and the output
voltage will track the input of the buffer. When the
accelerators activate the buffer connection is released
and the signal on each side of the buffer rises
independently. The accelerator current on both sides of
the buffer will be equal. If the pull-up resistance on both
sides of the buffer are also equal, then differences in the
rise time will be proportional to the difference in
capacitive loading on the two sides.
Because the signals on each side of the buffer rise
independently, the propagation delay can be positive or
negative. If the input side rises slowly relative to the
output (i.e., heavy capacitive loading on the input and
light load on the output) then the propagation delay t
is negative. If the output side rises slowly relative to the
input, t
For high to low transitions, there is a finite propagation
delay through the buffer from the time an external low
on the input drives the NMOS output low. This
propagation delay will always be positive because the
Typical Performance Curves
FIGURE 9. I
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
PLH
2.0
is positive.
(ISL33001)
2.5
CC1
T = +85°C
ENABLED CURRENT vs V
3.0
3.5
T = +25°C
10
V
CC1
4.0
(V)
T = -40°C
CC1
ISL33001, ISL33002, ISL33003
4.5
and V
5.0
CC1
CC2
5.5
supplies
C
Specified.
IN
6.0
PLH
= C
OUT
= 10pF, V
buffer connect threshold on the falling edge is below the
measurement points of the delay. In addition to the
propagation delay of the buffer, there will be additional
delay from the different capacitive loading of the buffer.
Figures 21 and 22 show how the propagation delay from
high to low, t
loading.
The buffer’s propagation delay times for rising and falling
edge signals must be taken into consideration for the
timing requirements of the system. SETUP and HOLD
times may need to be adjusted to take into account
excessively long propagation delay times caused by
heavy bus capacitances.
Pull-Up Resistor Selection
While the ISL33001, ISL33002, ISL33003 2-Channel
buffers are designed to improve the rise time of the bus
in passive pull-up systems, proper selection of the pull-
up resistor is critical for system operation when a buffer
is used. For a bus that is operating normally without
active rise time circuitry, using the ISL33001, ISL33002,
ISL33003 buffer will allow larger pull-up resistor values
to reduce sink currents when the bus is driving low.
However, choose a pull-up resistor value of no larger
than 20kΩ regardless of the bus capacitance seen on the
SDA/SCL lines. The Bus Idle or Stop Bit condition
requires valid logic high voltages to give a valid
connection state. Pull-up resistor values 20kΩ or smaller
are recommended to overcome the typical 150kΩ
impedance of the pre-charge circuitry, delivering valid
high levels.
FIGURE 10. I
600
550
500
450
400
350
300
250
200
150
100
2.0
CC1
= V
(ISL33001)
PHL
2.5
CC1
CC2
, is affected by V
DISABLED CURRENT vs V
3.0
= V
T = +85°C
CC
3.5
, T
A
V
CC1
= +25°C; Unless Otherwise
4.0
T = +25°C
(V)
CC
4.5
and capacitive
5.0
CC1
March 18, 2010
5.5
FN7560.0
6.0