isl54105 Intersil Corporation, isl54105 Datasheet
isl54105
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isl54105 Summary of contents
Page 1
... TMDS clock signal, creating an extremely clean, low-jitter DVI/HDMI signal that can be easily decoded by any TMDS receiver. The ISL54105 can be used as a cable extender, to clean up a noisy/jittery TMDS source provide a very stable TMDS signal to a finicky DVI or HDMI receiver. Block Diagram ...
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... Internal Pull-Up Resistance PU R Internal Pull-Down Resistance PD C Input Capacitance IN 2 ISL54105 ISL54105 Thermal Information Thermal Resistance (Typical, Note 1) +0.3V QFN Package Maximum Biased Junction Temperature . . . . . . . . . . . . . . . . +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0° ...
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... Operation up to 165MHz is guaranteed. While many parts will typically operate up to 225MHz, operation above 165MHz is not guaranteed SCL t SU:STA t HD:STA SDA IN SDA OUT 3 ISL54105 ISL54105 = 3.3V, pixel rate = 165MHz COMMENT Inputs driven by 165Mpixel/s TMDS signals. Default register settings All available inputs driven by 165Mpixel/s TMDS signals HIGH ...
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... ISL54105 Pin Configuration RES_TERM RES_BIAS RXC- 12 RXC RX0- 16 RX0 RESET ISL54105 ...
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... Ground return for the entire chip. The thermal pad must have a low impedance connection to GND for the ISL54105 to function at all. The lower electrical impedance, the better the ground, and the better the performance. A low thermal impedance between the thermal pad and the GND plane of the PCB will dissipate the heat from the package more efficiently as well and is recommended ...
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... Input Control (0x12) Recommended default: 0x63 6 ISL54105 BIT(S) FUNCTION NAME 3:0 Device Revision 1 = initial silicon second revision, etc. 7:4 Device ISL54105 1:0 Reserved Reserved 2 Activity Detect 0: TMDS clock not present on RXC 1: TMDS clock detected on RXC 3:0 Reserved This nibble should always be set to 0xC. 4 Reset Full chip reset ...
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... Output Options (0x00) 0x06 Data Output Drive (0x00) 0x07 Reserved (0xCC) 0x08 Equalization (0xCC) 0x09 Test Pattern Generator (0x00) 7 ISL54105 BIT(S) FUNCTION NAME 1:0 Reserved Set to 00. 2 Data Termination 0: TMDS Data inputs terminated into 50Ω (normal operation) 1: TMDS Data inputs terminated into 100Ω (for paralleled ...
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... PRBS7 Error Counter Link 1 (read only) 0x0C PRBS7 Error Counter Link 2 (read only) 0x10 PLL Bandwidth (0x10) Recommended default: 0x12 8 ISL54105 BIT(S) FUNCTION NAME 7:0 PRBS7 Error PRBS7 Error Counter of Link 0. Saturates at 0xFF. Reading Counter Link 0 this register clears this register at end of read ...
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... Application Information The ISL54105 is a TMDS regenerator, locking to the incoming DVI or HDMI signal with triple Clock Data Recovery units (CDRs) and a Phase Locked Loop (PLL). The PLL generates a low jitter pixel clock from the incoming TMDS clock. The TMDS data signals are equalized, sliced by the CDR, re-aligned to the PLL clock, and sent out the TMDS outputs ...
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... Tx pins are high impedance. In this state, they will draw no current from the Rx pins of any TMDS receiver they may be connected to. However, if power to the ISL54105 is removed, the Tx pins are no longer high-impedance. Figure 8 shows the relevant equivalent circuit, including the internal ESD protection diodes ...
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... V D (41, 53) V _ESD D Tx ISL54105 FIGURE 8. ISL54105 ESD PROTECTION DIODES This is non-ideal and can cause the ISL54105 to fail HDMI Compliance Test 7-3 (“V ”). V is the voltage across OFF OFF each 50Ω Rx resistor when the power is removed from the N device containing the ISL54105. ...
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... It does, however, limit the number of ISL54105s that can be put in series (although statistically unlikely that all the skews would line worst-case configuration) ...
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... Data on the serial bus must be valid for the entire time SCL is high (Figure 16). To achieve this, data being written to the ISL54105 is latched on a delayed version of the rising edge of SCL. SCL is delayed and deglitched inside the ISL54105 for three crystal clock periods (120ns for a 25MHz crystal) to eliminate spurious clock pulses that could disrupt serial communication ...
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... DATA STABLE Signals the beginning of serial I/O R/W ISL54105 Device Select Address Write The first 7 bits of the first byte select the ISL54105 on the 2-wire 0 ADDR1 ADDR0 bus at the address set by the ADDR[6:0} pins. The R/W bit indicating that the next transaction will be a write. ...
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... ISL54105 Signals the beginning of serial I/O R/W ISL54105 Device Select Address Write The first 7 bits of the first byte select the ISL54105 on the 2-wire 0 ADDR1 ADDR0 bus at the address set by the ADDR[6:0} pins. R indicating that the next transaction will be a write. ISL54105 Register Address Write ...
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... Tiebar shown (if present non-functional feature. The configuration of the pin #1 identifier is optional, but must be 6. located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 16 ISL54105 A EXPOSED PAD AREA X B 9.75 10.00 (68X 0.50) (72X 0 ...