isl22323 Intersil Corporation, isl22323 Datasheet - Page 13

• Manufacturer Part Number: isl22323
• Description: Dual Digitally Controlled Potentiometer Xdcp? , Low Noise, Low Power, I2c? Bus, 256 Taps
• Manufacturer: Intersil Corporation

The non-volatile IVRi and volatile WRi registers are
accessible with the same address.
The Access Control Register (ACR) contains information
and control bits described in Table 2.
The VOL bit (ACR[7]) determines whether the access to
wiper registers WRi or initial value registers IVRi.
If VOL bit is 0, the non-volatile IVRi registers are accessible.
If VOL bit is 1, only the volatile WRi are accessible. Note:
value is written to IVRi register also is written to the
corresponding WRi. The default value of this bit is 0.
The SHDN bit (ACR[6]) disables or enables Shut-down mode.
When this bit is 0, DCPs are in Shut-down mode. Default value
of the SHDN bit is 1.
The WIP bit (ACR[5]) is a read-only bit. It indicates that non-
volatile write operation is in progress. It is impossible to write
to the WRi or ACR while WIP bit is 1.
I
The ISL22323 supports an I
protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is a master and
the device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
2
NAME
ADDRESS
BIT #
C Serial Interface
(hex)
FIGURE 15. DCP CONNECTION IN SHUT-DOWN MODE
7
6
5
4
3
2
1
0
TABLE 2. ACCESS CONTROL REGISTER (ACR)
VOL
7
TABLE 1. MEMORY MAP (Continued)
SHDN
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
NON-VOLATILE
6
IVR1
IVR0
WIP
5
2
13
C bidirectional bus oriented
4
0
RHi
RWi
RLi
3
0
2
0
VOLATILE
WR1
WR0
N/A
N/A
N/A
N/A
N/A
N/A
1
0
0
0
ISL22323
transmit and receive operations. Therefore, the ISL22323
operates as a slave device in all applications.
All communication over the I
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line must change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (See
Figure 16). On power-up of the ISL22323, the SDA pin is in
the input mode.
All I
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL22323 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (See
Figure 16). A START condition is ignored during the power-
up of the device.
All I
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (See Figure 16). A STOP condition at the end
of a read operation, or at the end of a write operation places
the device in its standby mode.
An ACK (Acknowledge) is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (See Figure 17).
The ISL22323 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL22323 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation
A valid Identification Byte contains 10100 as the five MSBs,
and the following two bits matching the logic values present
at pins A1 and A0. The LSB is the Read/Write bit. Its value is
“1” for a Read operation and “0” for a Write operation (See
Table 3).
(MSB)
1
2
2
C interface operations must begin with a START
C interface operations must be terminated by a STOP
LOGIC VALUES AT PINS A1 AND A0, RESPECTIVELY
TABLE 3. IDENTIFICATION BYTE FORMAT
0
1
0
2
C interface is conducted by
0
A1
A0
May 31, 2007
FN6422.0
(LSB)
R/W