isl8500 Intersil Corporation, isl8500 Datasheet
isl8500
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isl8500 Summary of contents
Page 1
... Protection features include overcurrent, undervoltage and thermal overload protection integrated into the IC. The ISL8500 power good signal output indicates loss of regulation on the PWM output. ISL8500 is available in a small 4mmx3mm Dual Flat No-Lead (DFN) package. Ordering Information PART NUMBER PART TEMP ...
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... EN PG GND 2 ISL8500 R3 C3 301 100pF 10k 2.2nF 3.16k C1 10pF R2 C5 51.1k 0.1 μ F VIN PHASE ISL8500 BOOT VDD FIGURE 1. VIN RANGE FROM 5.5V TO 25V VOUT 5.5V TO 25V C9 10uF L 10μ H VOUT = 2.5V C10 C11 0.1 μ F 100 μ B340LB C13 1 µ F December 10, 2007 FN6611.0 ...
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... Functional Block Diagram VDD SOFT-START CONTROL 30µ VIN LDO VDD PG 3 ISL8500 VOLTAGE - + MONITOR EA 0.6V RAMP REFERENCE GENERATOR FAULT THERMAL MONITOR MONITOR OSCILLATOR +150°C OC MONITOR VDD POWER-ON RESET MONITOR EPAD GND VDD OC PWM MONITOR - + GATE VIN DRIVE POR VIN (x2) ...
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... Nominal Switching Frequency Modulator Gain Peak-to-Peak Sawtooth Amplitude PWM Ramp Offset Voltage Maximum Duty Cycle 4 ISL8500 Thermal Information Thermal Resistance QFN Package (Notes 1, 2 Ambient Temperature Range .-40°C to +85°C Junction Temperature Range .-40°C to +125°C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-free reflow profile ...
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... PG Propagation Delay PG Low Voltage PG Leakage Current SOFT-START SECTION Soft-Start Threshold to Enable Buck Soft-Start Threshold to Enable PG Soft-Start Voltage High Soft-Start Charging Current Soft-Start Pull-down POWER MOSFET r DS(ON) 5 ISL8500 SYMBOL TEST CONDITIONS GBWP SR COMP = 10pF Rising Edge Hysteresis T Rising Threshold SD T Hysteresis HYS ...
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... VDD (Pin 7) Internal 5V linear regulator output provides bias to all the internal control logic. The ISL8500 may be powered directly from a 5V (±10%) supply at this pin. When used supply input, this pin must be externally connected to VIN. The VDD pin must always be decoupled to GND with a ceramic bypass capacitor (minimum 1µ ...
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... OUTPUT LOAD (A) FIGURE 6. V REGULATION vs LOAD, 1.2V OUT 7 ISL8500 Unless otherwise noted, operating conditions are 100µ 2x22µF, I OUT 2 OUT power stage and the source for the internal linear regulator that provides bias for the IC. Place a ceramic capacitor from VIN to GND, close to the IC for decoupling (typical 10µF).” on page 6. ...
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... REGULATION vs LOAD, 3.3V OUT PHASE 5V/DIV VOUT RIPPLE 20mV/DIV IL 0.5A/DIV FIGURE 12. STEADY STATE OPERATION AT NO LOAD (5µs/DIV) 8 ISL8500 Unless otherwise noted, operating conditions are 100µ 2x22µ 2A. See “The input supply for the PWM regulator OUT 2 OUT power stage and the source for the internal linear regulator that provides bias for the IC. Place a ceramic capacitor from VIN to GND, close to the IC for decoupling (typical 10µ ...
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... EN 5V/DIV IL 1A/DIV FIGURE 16. SOFT-START AT FULL LOAD (2ms/DIV) VOUT 1V/DIV IL 2A/DIV PG 5V/DIV FIGURE 18. OUTPUT SHORT CIRCUIT (5µs/DIV) 9 ISL8500 Unless otherwise noted, operating conditions are 100µ 2x22µ 2A. See “The input supply for the PWM regulator OUT 2 OUT power stage and the source for the internal linear regulator that provides bias for the IC. Place a ceramic capacitor from VIN to GND, close to the IC for decoupling (typical 10µ ...
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... LDO has exceeded it’s POR threshold. The EN pin enables the buck controller portion of the ISL8500. When the voltage on the EN pin exceeds the POR rising threshold, the controller initiates the soft-start function for the PWM regulator. If the voltage on the EN pin drops below the POR falling threshold, the buck regulator shuts down ...
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... Thermal Overload Protection Thermal overload protection limits total power dissipation in the ISL8500. There is a sensor on the chip to monitor the junction temperature of the internal LDO and PWM switching power N-Channel MOSFET. When the junction temperature ( the sensor exceeds +150° ...
Page 12
... One of the parameters limiting the converter’s response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the ISL8500 will provide either 0% or 80% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level ...
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... F ESR = 2π The compensation network consists of the error amplifier (internal to the ISL8500) and the impedance networks Z and Z . The goal of the compensation network is to provide FB a closed loop transfer function with the highest 0dB crossing frequency (f ) and adequate phase margin. Phase margin ...
Page 14
... Careful component selection, tight layout of the critical components, and short, wide traces minimizes the magnitude of voltage spikes. There are two sets of critical components in the ISL8500 switching converter. The switching components are the most critical because they switch large amounts of energy, and therefore tend to generate large amounts of noise ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 15 ISL8500 L12.4x3 12 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE 2X (COMPLIANT TO JEDEC MO-229-VGED-4 ISSUE C) 0 ...