isl6334d Intersil Corporation, isl6334d Datasheet - Page 22

• Manufacturer Part Number: isl6334d
• Description: Vr11.1, 4-phase Pwm Controller With Phase Dropping, Droop Disabled And Load Current Monitoring Features
• Manufacturer: Intersil Corporation

The sensed current will flow out of the IMON pin and develop
a voltage across the resistor equivalent (R
resistance on the IMON pin reduces as the temperature
increases, the temperature impact on the IMON voltage can
be compensated. An NTC resistor can be placed close to the
power stage and used to form a R
temperature characteristics of the NTC, a resistor network is
needed to make the equivalent resistance on the IMON pin
reverse proportional to the temperature.
The external temperature compensation network can only
compensate the temperature impact on the IMON voltage,
while it has no impact to the sensed current inside ISL6334D.
Therefore, this network cannot compensate for the
temperature impact on the overcurrent protection function.
General Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to create a multiphase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced in the
following. In addition to this guide, Intersil provides complete
reference designs, which include schematics, bills of
materials, and example board layouts for all common
microprocessor applications.
Power Stages
The first step in designing a multiphase converter is to
determine the number of phases. This determination
depends heavily upon the cost analysis, which in turn
depends on system constraints that differ from one design to
the next. Principally, the designer will be concerned with
whether components can be mounted on both sides of the
circuit board; whether through-hole components are
permitted; and the total board space available for power
supply circuitry. Generally speaking, the most economical
solutions are those in which each phase handles between
15A and 25A. All surface-mount designs will tend toward the
lower end of this current range. If through-hole MOSFETs
and inductors can be used, higher per-phase currents are
possible. In cases where board space is the limiting
constraint, current can be pushed as high as 40A per phase,
but these designs require heat sinks and forced air to cool
the MOSFETs, inductors and heat-dissipating surfaces.
FIGURE 16. EXTERNAL TEMPERATURE COMPENSATION
o
C
22
IM O N
IMON
IN T E R N A L
IS L 6 3 3 4 D
C IR C U IT
. Due to the non-linear
IMON
). If the
ISL6334D
MOSFETs
The choice of MOSFETs depends on the current each
MOSFET will be required to conduct; the switching
frequency; the capability of the MOSFETs to dissipate heat;
and the availability and nature of heat sinking and air flow.
LOWER MOSFET POWER CALCULATION
The calculation for heat dissipated in the lower MOSFET is
simple, since virtually all of the heat loss in the lower
MOSFET is due to current conducted through the channel
resistance (r
continuous output current; I
current (see Equation 1); d is the duty cycle (V
L is the per-channel inductance.
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the
dead time when inductor current is flowing through the
lower-MOSFET body diode. This term is dependent on the
diode forward voltage at I
frequency, F
the beginning and the end of the lower-MOSFET conduction
interval respectively.
Thus the total maximum power dissipated in each lower
MOSFET is approximated by the summation of P
P
UPPER MOSFET POWER CALCULATION
In addition to r
MOSFET losses are due to currents conducted across the
input voltage (V
higher portion of the upper MOSFET losses are dependent on
switching frequency, the power calculation is more complex.
Upper MOSFET losses can be divided into separate
components involving the upper MOSFET switching times;
the lower MOSFET body-diode reverse-recovery charge, Q
and the upper MOSFET r
When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 23,
the required time for this commutation is t
approximated associated power loss is P
P
P
P
LOW,2
LOW 1
LOW 2
UP 1 ,
,
,
≈
.
V
=
=
IN
r
V
⎛
⎝
DS ON
DS(ON)
sw
D ON
I
----- -
N
M
(
DS(ON)
(
; and the length of dead times, t
+
IN
I
-------- -
) during switching. Since a substantially
)
PP
2
)
F
). In Equation 21, I
⎛
⎜
⎝
sw
⎞ t
⎠
I
----- -
N
⎛
⎜
⎝
M
losses, a large portion of the upper
----
2
⎞
⎟
⎠
1
⎛
⎝
2
I
----- -
⎞
⎟
⎠
N
M
DS(ON)
(
M
f
1 d
S
+
, V
PP
–
I
-------- -
PP
2
D(ON)
)
is the peak-to-peak inductor
+
⎞ t
⎠
conduction loss.
I
--------------------------------
L PP
d1
,
2
; the switching
+
12
M
(
⎛
⎜
⎝
1 d
I
----- -
N
is the maximum
M
–
UP,1
1
–
and the
)
I
-------- -
PP
2
.
OUT
d1
⎞
⎟
⎠
October 29, 2008
t
d2
LOW,1
and t
/V
IN
(EQ. 21)
(EQ. 22)
(EQ. 23)
FN6802.0
); and
d2
and
, at
rr
;