isl6622 Intersil Corporation, isl6622 Datasheet - Page 5

• Manufacturer Part Number: isl6622
• Description: Vr11.1, 4-phase Pwm Controller With Light Load Efficiency Enhancement And Load Current Monitoring
• Manufacturer: Intersil Corporation

Electrical Specifications
Functional Pin Description
Three-State Upper Gate Falling Threshold (Note 4)
UGATE Rise Time (Note 4)
LGATE Rise Time (Note 4)
UGATE Fall Time (Note 4)
LGATE Fall Time (Note 4)
UGATE Turn-On Propagation Delay (Note 4)
LGATE Turn-On Propagation Delay (Note 4)
UGATE Turn-Off Propagation Delay (Note 4)
LGATE Turn-Off Propagation Delay (Note 4)
Diode Braking Holdoff Time (Note 4)
Minimum LGATE ON-Time At Diode Emulation
OUTPUT (Note 4)
Upper Drive Source Current
Upper Drive Source Impedance
Upper Drive Sink Current
Upper Drive Sink Impedance
Lower Drive Source Current
Lower Drive Source Impedance
Lower Drive Sink Current
Lower Drive Sink Impedance
PACKAGE PIN #
SOIC
1
2
3
4
5
6
7
8
-
-
-
DFN
10
11
1
2
3
4
5
6
7
8
9
PARAMETER
SYMBOL
GD_SEL
PHASE
UGATE
LGATE
BOOT
UVCC
LVCC
PWM
GND
VCC
PAD
PIN
Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.
Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See “Internal Bootstrap
Device” on page 8 for guidance in choosing the capacitor value.
This pin sets the LG drive voltage in PSI mode.
The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation,
see the three-state PWM Input section on page 6 for further details. Connect this pin to the PWM output of the
controller.
Bias and reference ground. All signals are referenced to this node. It is also the power ground return of the driver.
Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
This pin provides power for the LGATE drive. Place a high quality low ESR ceramic capacitor from this pin to GND.
This pin provides power to the upper gate drive. Its operating range is +5V to 12V. Place a high quality low ESR
ceramic capacitor from this pin to GND.
Connect this pin to 12V bias supply. This pin supplies power to the upper gate in the SOIC and to the LDO for the
lower gate drive. Place a high quality low ESR ceramic capacitor from this pin to GND.
Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides
a return path for the upper gate drive.
Connect this pad to the power ground plane (GND) via thermally enhanced connection.
5
Recommended Operating Conditions. Parameters with MIN and/or MAX limits are 100% tested at +25°C,
unless otherwise specified. Temperature limits established by characterization and are not
production tested (Continued)
R
t
R
I
UG_OFF_DB
t
I
LG_ON_DM
U_SOURCE
L_SOURCE
SYMBOL
U_SOURCE
L_SOURCE
R
R
I
I
U_SINK
t
L_SINK
t
t
t
U_SINK
L_SINK
PDHU
PDHL
PDLU
PDLL
t
t
t
t
RU
RL
FU
FL
ISL6622
VCC = 12V
V
V
V
V
V
V
V
V
V
V
V
20mA Source Current
V
20mA Sink Current
V
20mA Source Current
V
20mA Sink Current
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
= 12V, 3nF Load, 10% to 90%
= 12V, 3nF Load, 10% to 90%
= 12V, 3nF Load, 90% to 10%
= 12V, 3nF Load, 90% to 10%
= 12V, 3nF Load, Adaptive
= 12V, 3nF Load, Adaptive
= 12V, 3nF Load
= 12V, 3nF Load
= 12V
= 12V
= 12V, 3nF Load
= 12V, 3nF Load
= 12V, 3nF Load
= 12V, 3nF Load
TEST CONDITIONS
FUNCTION
MIN
230
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.25
1.35
1.35
0.90
TYP
330
2.8
2.0
26
18
18
12
20
10
10
10
60
2
2
3
MAX
450
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
October 30, 2008
UNITS
FN6470.2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Ω
Ω
Ω
Ω
V
A
A
A
A