isl62391 Intersil Corporation, isl62391 Datasheet - Page 17

• Manufacturer Part Number: isl62391
• Description: High-efficiency, Triple-output System Power Supply Controller For Notebook Computers
• Manufacturer: Intersil Corporation

Selection of the Input Capacitor
The important parameters for the bulk input capacitance are
the voltage rating and the RMS current rating. For reliable
operation, select bulk capacitors with voltage and current
ratings above the maximum input voltage and capable of
supplying the RMS current required by the switching circuit.
Their voltage rating should be at least 1.25x greater than the
maximum input voltage, while a voltage rating of 1.5x is a
preferred rating. Figure 28 is a graph of the input RMS ripple
current (normalized relative to output load current) as a
function of duty cycle and is adjusted for a converter efficiency
of 80%. The ripple current calculation is written as
Equation 21:
Where:
In addition to the bulk capacitance, some low ESL ceramic
capacitance is recommended to decouple between the drain
of the high-side MOSFET and the source of the low-side
MOSFET.
MOSFET Selection and Considerations
Typically, a MOSFET cannot tolerate even brief excursions
beyond their maximum drain to source voltage rating. The
MOSFETs used in the power stage of the converter should
have a maximum V
upper voltage tolerance of the input power source and the
voltage spike that occurs when the MOSFET switches off.
I
IN_RMS NORMALIZED
- I
- x is a multiplier (0 to 1) corresponding to the inductor
- D is the duty cycle that is adjusted to take into account
D
peak-to-peak ripple amplitude expressed as a
percentage of I
the efficiency of the converter which is written as
Equation 22.
MAX
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
FIGURE 28. NORMALIZED RMS INPUT CURRENT
=
0
,
0
------------------------- -
V
is the maximum continuous I
IN
V
⋅
0.1
O
EFF
0.2
DS
MAX
0.3
=
rating that exceeds the sum of the
(0% to 100%)
(
D D
0.4
DUTY CYCLE
x = 1
x = 0.75
x = 0.50
x = 0.25
x = 0
17
–
2
0.5
)
+
⎛
⎝
D
0.6
LOAD
⋅
----- -
12
x
2
0.7
⎞
⎠
of the converter
0.8
ISL62391, ISL62392
0.9
(EQ. 21)
(EQ. 22)
1.0
There are several power MOSFETs readily available that are
optimized for DC/DC converter applications. The preferred
high-side MOSFET emphasizes low gate charge so that the
device spends the least amount of time dissipating power in
the linear region. Unlike the low-side MOSFET, which has
the drain-source voltage clamped by its body diode during
turn off, the high-side MOSFET turns off with a V
approximately V
preferred low-side MOSFET emphasizes low r
fully saturated to minimize conduction loss. It should be
noted that this is an optimal configuration of MOSFET
selection for low duty cycle applications (D < 50%). For
higher output, low input voltage solutions, a more balanced
MOSFET selection for high- and low-side devices may be
warranted.
For the low-side (LS) MOSFET, the power loss can be
assumed to be conductive only and is written as Equation 23:
For the high-side (HS) MOSFET, the conduction loss is
written as Equation 24:
For the high-side MOSFET, the switching loss is written as
Equation 25:
Where:
Selecting The Bootstrap Capacitor
The selection of the bootstrap capacitor is written as
Equation 26:
Where:
P
P
P
C
CON_LS
CON_HS
SW_HS
BOOT
- I
- I
- t
- t
- Q
- ΔV
inductor current minus 1/2 of the inductor ripple current
current plus 1/2 of the inductor ripple current
saturation
high-side MOSFET
the boot capacitor each time the high-side MOSFET is
switched on
VALLEY
PEAK
ON
OFF
g
BOOT
is the total gate charge required to turn on the
=
is the time required to drive the device into
=
≈
is the time required to drive the device into cut-off
----------------------- -
ΔV
=
is the sum of the DC component of the inductor
I
V
---------------------------------------------------------------- -
LOAD
I
, is the maximum allowed voltage decay across
IN
Q
BOOT
LOAD
is the difference of the DC component of the
g
•
I
IN
VALLEY
2
- V
2
r ⋅
•
DS ON
r
OUT
DS ON
2
(
(
•
t
, plus the spike across it. The
ON
)_LS
)_HS
•
f
SW
•
(
•
1 D
D
+
–
V
------------------------------------------------------------ -
IN
)
•
I
PEAK
2
•
DS(ON)
December 22, 2008
t
OFF
DS
(EQ. 25)
•
of
(EQ. 23)
(EQ. 24)
(EQ. 26)
f
SW
FN6666.4
when