isl6252a Intersil Corporation, isl6252a Datasheet - Page 20

• Manufacturer Part Number: isl6252a
• Description: Highly Integrated Battery Charger Controller For Notebook Computers
• Manufacturer: Intersil Corporation

The loop response equations, bode plots and the selection
of C
with loop gain reduced by the duty cycle and the ratio of
R
D = 50%, the loop gain will be 6dB lower than the loop gain
in Figure 20. This gives lower cross over frequency and
higher phase margin in this mode. If R
duty cycle is 50% then the adapter current loop gain will be
identical to the gain in Figure 20.
A filter should be added between R
reduce switching noise. The filter roll off frequency should be
between the cross over frequency and the switching
frequency (~100kHz).
Voltage Control Loop
When the battery is charged to the voltage set by CELLS and
VADJ the voltage error amplifier (gm1) takes control of the
output (assuming that the adapter current is below the limit set
by ACLIM). The voltage error amplifier (gm1) discharges the
cap on VCOMP to limit the output voltage. The current to the
battery decreases as the cells charge to the fixed voltage and
the voltage across the internal battery resistance decreases.
As battery current decreases the 2 current error amplifiers
(gm2 and gm3) output their maximum current and charge the
capacitor on ICOMP to its maximum voltage (limited to 1.2V
above VCOMP). With high voltage on ICOMP, the minimum
voltage buffer output equals the voltage on VCOMP. The
voltage control loop is shown in Figure 22.
.
Output LC Filter Transfer Functions
The gain from the phase node to the system output and
battery depend entirely on external components. Typical
S1
VCOMP
ICOMP
/R
C VCOMP
R VCOMP
S2
. In other words, if R
Σ
are the same as the charge current control loop
FIGURE 22. VOLTAGE CONTROL LOOP
11
0.25
2.1V
gm1
+
-
-
+
PHASE
+
-
R FET_r
CA2
R4
20
20
S1
R3
+
-
= R
DS(ON)
S1
S2
CSON
CSOP
and CSIP and CSIN to
and the duty cycle
S1
L
/R
S2
R L_DCR
C F2
C O
R ESR
= 2 and the
R F2
ISL6252, ISL6252A
R S2
R BAT
output LC filter response is shown in Figure 23. Transfer
function A
A
The resistance R
inductor DCR, R
battery (normally between 50mΩ and 200mΩ). The worst
case for voltage mode control is when the battery is absent.
This results in the highest Q of the LC filter and the lowest
phase margin.
The compensation network consists of the voltage error
amplifier gm1 and the compensation network R
C
frequency pole and a zero at f
information is added to the feedback to create a second
zero, f
and ISL6252 add a pole at f
divider resistors that set the DC output voltage. For a 3-cell
battery, R
40, 41 and 42 relate the compensation network’s poles,
zeros and gain to the components in Figure 22. Figure 24
shows an asymptotic bode plot of the DC/DC converter’s
gain vs frequency. It is strongly recommended that f
approximately 30% of f
of f
ω
LC
ESR
FIGURE 23. FREQUENCY RESPONSE OF THE LC OUTPUT
VCOMP
LC
=
.
ZERO2
=
---------------------------------------------------------- -
⎛
⎜
⎝
----------- -
ω
R
-------------------------------- -
(
, which give the loop very high DC gain, a very low
s
DP
R
BATTERY
3
2
LC
ESR
R
= 320kΩ and R
⎛
⎝
(s) is shown in Equation 36:
+
BATTERY
1
. The low pass filter R
FILTER
1
–
------------------------ -
(
ω
⋅
---------------
ω
LC
C
SENSE
O
ESR
= 200mΩ
s
s
o
is a combination of MOSFET r
)
⋅
Q
= 50mΩ
⎞
⎠
)
LC
ω
+
and the internal resistance of the
LC
1
and f
FREQUENCY
⎞
⎟
⎠
4
=
FILTER
= 64kΩ. Equations 37, 38, 39,
ZERO1
----------------------- -
(
ZERO2
L C
1
⋅
F2
. R
o
, C
. Inductor current
)
3
is approximately 70%
F2
and R
Q
between R
NO BATTERY
=
4
R
are internal
VCOMP
o
DS(ON)
⋅
ZERO1
July 19, 2007
------ -
C
(EQ. 36)
L
SENSE
FN6498.1
o
,
,
is