isl6530 Intersil Corporation, isl6530 Datasheet - Page 12
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isl6530
Manufacturer Part Number
isl6530
Description
Dual 5v Synchronous Buck Pulse-width Modulator Pwm Controller For Ddram Memory Vddq And Vtttermination
Manufacturer
Intersil Corporation
Datasheet
1.ISL6530.pdf
(17 pages)
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Compensation Break Frequency Equations
Figure 9 shows an asymptotic plot of the DC-DC converter’s
gain vs frequency. The actual modulator gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 9. Using the above guidelines should give a
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at F
amplifier. The closed loop gain is constructed on the graph of
Figure 9 by adding the modulator gain (in dB) to the
compensation gain (in dB). This is equivalent to multiplying
the modulator transfer function to the compensation transfer
function and plotting the gain.
The compensation gain uses external impedance networks
Z
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
.
DV
F
F
FB
Z1
Z2
FIGURE 8. VOLTAGE-MODE BUCK CONVERTER
OSC
and Z
=
=
--------------------------------- -
2π
------------------------------------------------------ -
2π x R
OSC
IN
×
R
(
COMPARATOR
1
to provide a stable, high bandwidth (BW) overall
2
COMPENSATION DESIGN
ERROR
AMP
1
DETAILED COMPENSATION COMPONENTS
V
×
ISL6530
+
E/A
1
C
PWM
R
2
Z
+
3
-
FB
-
+
) x C
COMP
C
REFERENCE
P2
2
REFERENCE
3
C
with the capabilities of the error
+
1
-
DRIVER
DRIVER
R
12
Z
2
F
F
IN
P1
P2
FB
=
=
Z
FB
-------------------------------------------------------- -
2π x R
----------------------------------- -
2π x R
PHASE
(PARASITIC)
V
C
IN
3
1
L
Z
R
2
3
IN
O
1
x
x C
R
ESR
1
C
3
C
--------------------- -
C
O
3
V
1
1
OUT
x C
+
C
V
2
OUT
2
ISL6530
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
Modern digital ICs can produce high transient load slew
rates. High-frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors.
The bulk filter capacitor values are generally determined by
the ESR (effective series resistance) and voltage rating
requirements rather than actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient. An
aluminum electrolytic capacitor’s ESR value is related to the
case size with lower ESR available in larger case sizes.
However, the equivalent series inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient loading.
Unfortunately, ESL is not a specified parameter. Work with
your capacitor supplier and measure the capacitor’s
impedance with frequency to select a suitable component. In
most cases, multiple electrolytic capacitors of small case size
perform better than a single large case capacitor.
FIGURE 9. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
100
-20
-40
-60
80
60
40
20
0
10
MODULATOR
20
log
GAIN
100
R2
------- -
R1
F
Z1
F
1K
LC
F
FREQUENCY (Hz)
Z2
F
ESR
10K
F
P1
100K
F
P2
1M
ERROR AMP GAIN
COMPENSATION
20
OPEN LOOP
November 15, 2004
LOOP GAIN
log
10M
GAIN
--------------- -
V
V
FN9052.2
OSC
IN