LDS-L9D340G64BG2 LOGIC Devices Incorporated, LDS-L9D340G64BG2 Datasheet - Page 120

• Manufacturer Part Number: LDS-L9D340G64BG2
• Description: 4.0 Gb, Ddr3, 64 M X 64 Integrated Module Imod
• Manufacturer: LOGIC Devices Incorporated

LOGIC Devices Incorporated
Figure 71 - Method for Calculating
t HZ (DQS), t HZ (DQ)
Notes:
t HZ (DQS), t HZ (DQ) end point = 2 × T1 - T2
1. Within a burst, the rising strobe edge is not necessarily fixed at
2. The DQS high pulse width is defined by
3. The minimum pulse width of the READ preamble is defined by
(MAX). Instead, the rising strobe edge can vary between
t
case) and
case); however, they tend to track one another.
pulse width of the READ postamble is defined by
QSL. Likewise,
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t
LZ (DQS) MAX and
T1
t
LZ (DQS) MIN and
T2
t
LZ and
V
V
V
V
OH
OH
OL
OL
t
HZ (DQS) MAX are not tied to
+ 2xmV
+ xmV
t
- xmV
- 2xmV
HZ
4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD)
t
HZ (DQS) MIN are not tied to
120
t
QSH, and the DQS low pulse width is defined by
V
V
PRELIMINARY INFORMATION
V
TT
V
t
TT
RPST (MIN).
TT
TT
+ 2xmV
- 2xmV
+ xmV
t LZ (DQS), t LZ (DQ) begin point = 2 × T1 - T2
- xmV
High Performance, Integrated Memory Module Product
t
DQSCK (MIN) and
t
t
t
DQSCK (MAX) (late strobe
RPRE (MIN). The minimum
DQSCK (MIN) or
T1
t
DQSCK (MIN) (early strobe
T2
t LZ (DQS), t LZ (DQ)
t
DQSCK (MAX).
L9D340G64BG2
t
DQSCK
Jun 08, 2010 LDS-L9D340G64BG2-B