ir3508z International Rectifier Corp., ir3508z Datasheet - Page 12

• Manufacturer Part Number: ir3508z
• Description: Xphase3 Phase Ic
• Manufacturer: International Rectifier Corp.

A synchronous rectification disable comparator is used to detect the converter’s CSIN- pin voltage, which
represents local converter output voltage. If the voltage is below 75% of VDAC and negative current is detected,
GATEL is driven low, which disables synchronous rectification and eliminates negative current during power-up.
The gate drivers are pulled low if the supply voltage falls below the normal operating range. An 80k
connected across the GATEH/GATEL and PGND pins to prevent the GATEH/GATEL voltage from rising due to
leakage or other causes under these conditions.
PWM Ramp
Every time the phase IC is powered up, the PWM ramp magnitude is calibrated to generate a 52.5 mV/% ramp
(VCC=12V). For example, a 15 % duty ratio will generate a ramp amplitude of 787.5 mV (15 x 52.5 mV) with 12V
supply applied to VCC. Feed-forward control is achieved by varying the PWM ramp proportionally with VCC
voltage after calibration.
Debugging Mode
From a system perspective, the PSI input is controlled by the system and is forced low when the load current is
lower than a preset limit and forced high when load current is higher than the preset limit. IR3508Z can accept an
active low signal on its PSI input and force the drivers into tri-state, effectively, forcing the phase IC into an off
state. A PSI-assert signal activates three features in the Phase IC. First, it disconnects the IOUT pin from the
ISHARE bus (from a system perspective). ISHARE is used to report current and is used for over-current
protection. By disconnecting the disabled phase from the ISHARE bus, proper current reporting and over-current
protection level are ensured. Secondly, the D Flip-Flop (DFF) is disabled, bypassing the Phase IC from the daisy
chain loop. By removing the DFF from the daisy chain, the system ensures that proper phase delay is activated
among the active phases. Finally, the gate drivers are forced to tri-state, disabling the phase IC from the power
stage. Figure 6 shows the impact of PSI-assert on the gate drivers. After an 8 cycle PHSIN delay followed by a
CLK falling edge, the PSI_SYNC goes from 0 to 1. This disables the gate drives and the DFF.
If the CSIN+ pin is pulled up to VCCL voltage, IR3508Z enters into debugging mode. Both drivers are pulled low
and IOUT output is disconnected from the current share bus, which isolates this phase IC from other phases.
However, the phase timing from PHSIN to PHSOUT does not change .
Power State Indicator (PSI) function
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D_PWM LATCH
PSI_SYNC
PSI
CLK
Figure 6: PSI assertion.
8 PHSIN Delay
Jan 09, 2009
IR3508Z
resistor is