ltc1760 Linear Technology Corporation, ltc1760 Datasheet - Page 39

• Manufacturer Part Number: ltc1760
• Description: Dual Smart Battery System Manager
• Manufacturer: Linear Technology Corporation

APPLICATIO S I FOR ATIO
3. Voltage tracking for the discharge process does not
The LTC1760 has two transient conditions that force the
discharge path P-channel MOSFETs to have two additional
parameters to consider. The parameters are gate charge
Q
When the LTC1760 senses a LOW_POWER event, all the
P-channel MOSFETs are turned on simultaneously to
allow voltage recovery due to a loss of a given power
source. However, there is a delay in the time it takes to turn
on all the MOSFETs. Slow MOSFETs will require more bulk
capacitance to hold up all the system’s power supply
function during the transition and fast MOSFET will require
less bulk capacitance. The transition speed of a MOSFET
to an on or off state is a direct function of the MOSFET gate
charge.
I
LTC1760 and “t” is the time it takes to move that charge to
a new state and change the MOSFET conduction mode.
Hence time is directly related to Q
up with MOSFETs of lower R
MOSFETs has a counterproductive increase in gate charge
making the MOSFET slower. Please note that the LTC1760
recovery time specification only refers to the time it takes
for the voltage to recover to the level just prior to the
LOW_POWER event as opposed to full voltage.
The single pulse current rating of MOSFET is important
when a short-circuit takes place. The MOSFET must
survive a 15ms overload. MOSFETs of lower R
MOSFETs that use more powerful thermal packages will
have a high power surge rating. Using too small of a pulse
rating will allow the MOSFET to blow to the open circuit
condition instantly like a fuse. Typically there is no
outward sign of failure because it happens so fast. Please
measure the surge current for all discharge power paths
under worse case conditions and consult the MOSFET
data sheet for the limitations. Voltage sources with the
highest voltage and the most bulk capacitance are often
the biggest risk. Specifically the MOSFETs in the wall
DRIVE
GATE
C/10 or less which is well within the linear operation
range of the MOSFETs.
need such precise voltage tracking values.
t = Q
and single pulse power capability.
is the fixed drive current into the gate from the
GATE
/I
DRIVE
U
U
DS(ON)
GATE
W
. Since Q
, choosing such
U
GATE
DS(ON)
goes
or
Unique Configuration Information
This section summarizes unique LTC1760 configurations
that allow some LTC1760 features to be eliminated. These
configurations may be selected in any combination with-
out adversely affecting LTC1760 operation. Refer to the
Typical Application circuit diagram located at the back of
this data sheet.
adapter path with wall adapters of high voltage, large bulk
capacitance and low resistance DC cables between the
adapter and device are the most common failures.
Remember to only use the real wall adapter with a produc-
tion DC power cord when performing the wall adapter path
test. The use of a laboratory power supply is unrealistic for
this test and will force you to over specify the MOSFET
ratings. A battery pack usually has enough series resis-
tance to limit the peak current or are too low in voltage to
create enough instantaneous power to damage their re-
spective power path MOSFETs.
Conditioning Systems With Large Loads
In systems where the load is too large to be used for
conditioning a single battery it may be necessary to
bypass the built in calibrate function and simply switch in
an external load. A convenient way to accomplish this task
is by using an SMBus based LTC1623 load switch control-
ler. See Figure 10.
TO/FROM
SMBus
HOST
SMBus
LTC1760
LTC1623
CHARGE
Figure 10
MUX
PowerPath
MUX
LTC1760
TO
LOAD
CONDITIONING
LOAD
1760 F10
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