ltc1196-2bcs8-trpbf Linear Technology Corporation, ltc1196-2bcs8-trpbf Datasheet - Page 18

• Manufacturer Part Number: ltc1196-2bcs8-trpbf
• Description: 8-bit, So-8, 1msps Adcs With Auto-shutdown Options
• Manufacturer: Linear Technology Corporation

LTC1196/LTC1198
APPLICATIONS INFORMATION
Clock Frequency
The maximum recommended clock frequency is 14.4MHz
at 25°C for the LTC1196/LTC1198 running off a 5V supply.
With the supply voltage changing, the maximum clock fre-
quency for the devices also changes (see the typical curve
of Maximum Clock Rate vs Supply Voltage). If the supply
is reduced, the clock rate must be reduced also. At 3V the
devices are specifi ed with a 5.4MHz clock at 25°C.
Mixed Supplies
It is possible to have a digital system running off a 5V supply
and communicate with the LTC1196/LTC1198 operating on
a 3V supply. Achieving this reduces the outputs of D
from the ADCs to toggle the equivalent input of the digital
system. The CS, CLK and D
5V signals from the digital system without causing any
problem (see typical curve of Digital Input Logic Threshold
vs Supply Voltage). With the LTC1196 operating on a 3V
supply, the output of D
This signal easily meets TTL levels (see Figure 6).
COMMON MODE RANGE
BOARD LAYOUT CONSIDERATIONS
Grounding and Bypassing
The LTC1196/LTC1198 are easy to use if some care is
taken. They should be used with an analog ground plane
and single-point grounding techniques. The GND pin
should be tied directly to the ground plane.
The V
1μF tantalum with leads as short as possible. If the power
18
DIFFERENTIAL INPUTS
Figure 6. Interfacing a 3V Powered LTC1196 to a 5V System
CC
pin should be bypassed to the ground plane with a
0V TO 3V
CS
+IN
–IN
GND
LTC1196
OUT
only goes between 0V and 3V.
IN
D
V
CLK
V
OUT
REF
inputs of the ADCs will take
CC
3V
3V
4.7μF
P1.4
P1.3
P1.2
(e.g., 8051)
MPU
1196/98 F06
OUT
5V
supply is clean, the LTC1196/LTC1198 can also operate
with smaller 0.1μF surface mount or ceramic bypass ca-
pacitors. All analog inputs should be referenced directly to
the single-point ground. Digital inputs and outputs should
be shielded from and/or routed away from the reference
and analog circuitry.
SAMPLE-AND-HOLD
Both the LTC1196 and the LTC1198 provide a built-in
sample-and-hold (S&H) function to acquire the input
signal. The S&H acquires the input signal from “+” input
during t
LTC1198 can sample input signals in either single-ended
or differential mode (see Figure 7).
Single-Ended Inputs
The sample-and-hold of the LTC1198 allows conversion
of rapidly varying signals. The input voltage is sampled
during the t
interval begins as the bit preceding the fi rst DUMMY bit is
shifted in and continues until the falling CLK edge after the
second DUMMY bit is received. On this falling edge, the
S&H goes into hold mode and the conversion begins.
Differential Inputs
With differential inputs, the ADC no longer converts just a
single voltage but rather the difference between two volt-
ages. In this case, the voltage on the selected “+” input
is still sampled and held and therefore may be rapidly
time varying just as in single-ended mode. However, the
voltage on the selected “–” input must remain constant
and be free of noise and ripple throughout the conversion
time. Otherwise, the differencing operation may not be
performed accurately. The conversion time is 8.5 CLK
cycles. Therefore, a change in the “–” input voltage during
this interval can cause conversion errors. For a sinusoidal
voltage on the “–” input, this error would be:
where f(“–”) is the frequency of the “–” input voltage, V
is its peak amplitude and f
V
ERROR(MAX)
SMPL
SMPL
as shown in Figures 1 and 2. The S&H of the
= V
time as shown in Figure 7. The sampling
PEAK
• 2 • π • f(“–”) • 8.5/fCLK
CLK
is the frequency of the CLK.
119698fa
PEAK