ltc1196-2bcs8-trpbf Linear Technology Corporation, ltc1196-2bcs8-trpbf Datasheet - Page 19

• Manufacturer Part Number: ltc1196-2bcs8-trpbf
• Description: 8-bit, So-8, 1msps Adcs With Auto-shutdown Options
• Manufacturer: Linear Technology Corporation

APPLICATIONS INFORMATION
V
to f
1/4LSB error (5mV) with the converter running at CLK =
12MHz, its peak value would have to be 18.7V.
ANALOG INPUTS
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1196/LTC1198
have one capacitive switching input current spike per
conversion. These current spikes settle quickly and do
not cause a problem. However, if source resistances larger
than 100Ω are used or if slow settling op amps drive the
inputs, care must be taken to insure that the transients
caused by the current spikes settle completely before the
conversion begins.
ERROR
CLK
. For a 60Hz signal on the “–” input to generate a
is proportional to f(“–”) and inversely proportional
“+” INPUT
“–” INPUT
D
CLK
OUT
D
CS
IN
START
Figure 7. LTC1198 “+” and “–” Input Settling Windows
SGL/DIFF
ODD/SIGN
S
A
M
P
E L
1ST BIT TEST “–” INPUT MUST
“+” Input Settling
The input capacitor of the LTC1196 is switched onto “+”
input at the end of the conversion and samples the input
signal until the conversion begins (see Figure 1). The input
capacitor of the LTC1198 is switched onto “+” input during
the sample phase (t
is 2.5 CLK cycles before conversion starts. The voltage on
the “+” input must settle completely within t
LTC1196/LTC1198. Minimizing R
input settling time. If a large “+” input source resistance
must be used, the sample time can be increased by allow-
ing more time between conversions for the LTC1196 or by
using a slower CLK frequency for the LTC1198.
SETTLE DURING THIS TIME
DUMMY
“+” INPUT MUST
SETTLE DURING
THIS TIME
t
SMPL
DUMMY
H
SMPL
O
LTC1196/LTC1198
L
D
, see Figure 7). The sample phase
t
CONV
DON’T CARE
SOURCE
+
will improve the
1196/98 F07
B7
SMPL
19
for the
119698fa