ltc1967 Linear Technology Corporation, ltc1967 Datasheet - Page 14
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ltc1967
Manufacturer Part Number
ltc1967
Description
Precision Extended Bandwidth, Rms-to-dc Converter
Manufacturer
Linear Technology Corporation
Datasheet
1.LTC1967.pdf
(28 pages)
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APPLICATIO S I FOR ATIO
LTC1967
100mV to 110mV (+10%) and back (–10%), the step
responses are essentially the same as a standard expo-
nential rise and decay between those two levels. In such
cases, the time constant of the decay will be in between
that of the rising edge and falling edge cases of Figure 10.
Therefore, the worst case is the falling edge response as
it goes to zero, and it can be used as a design guide.
Figure 11 shows the settling accuracy vs settling time for
a variety of averaging capacitor values. If the capacitor
value previously selected (based on error requirements)
gives an acceptable settling time, your design is done.
14
0.1
10
1
0.01
Figure 10a. LTC1967 Rising Edge with C
120
100
80
60
40
20
0
0
C
AVE
= 1 F
0.05
C = 0.1 F
U
0.1
TIME (SEC)
U
C = 0.22 F
0.15
0.1
W
0.2
C = 0.47 F
Figure 11. Settling Time with One Cap Averaging
1967 F10a
0.25
AVE
= 1 F
C = 1 F
U
SETTLING TIME (SEC)
C = 2.2 F
1
But with 100 F, the settling time to even 10% is a full 20
seconds, which is a long time to wait. What can be done
about such a design? If the reason for choosing 100 F is
to keep the DC error with a 100mHz input less than 0.1%,
the answer is: not much. The settling time to 1% of 32
seconds is just 3.2 cycles of this extremely low frequency.
Averaging very low frequency signals takes a long time.
However, if the reason for choosing 100 F is to keep the
peak error with a 10Hz input less than 0.1%, there is
another way to achieve that result with a much improved
settling time.
C = 4.7 F
Figure 10b. LTC1967 Falling Edge with C
120
100
80
60
40
20
0
C = 10 F
0
C
AVE
= 1 F
0.1
C = 22 F
0.2
TIME (SEC)
10
0.3
C = 47 F
0.4
1967 F10b
C = 100 F
AVE
0.5
= 1 F
1966 F12
100
1967f