mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 479

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
as RSTI is asserted and remains asserted for 32,768 CLKIN cycles after RSTI is negated.
For proper normal reset operation, DRESETEN must be negated as long as RSTI is
asserted.
The levels of the mode select inputs, QSPI_Dout/WSEL, QSPI_CLK/BUSW1, and
QSPI_CS0/BUSW0, are sampled when RSTI negates and select the port size of CS0 and
the physical data bus width after a master reset occurs. The INTx signals are synchronized
and are registered on the last falling edge of CLKIN where RSTI is asserted.
During the normal reset period, all outputs are driven to their default levels. Once RSTO
negates, all bus signals continue to remain in this state until the ColdFire core begins the
first bus cycle for reset exception processing.
A normal reset causes all bus activity except SDRAM refresh cycles to terminate. During
a normal reset, SDRAM refresh cycles continue to occur at the programmed rate and with
the programmed waveform timing. In addition, normal reset initializes registers
appropriately for a reset exception. During a normal reset, SCR[RSTSRC] is set to 0b01 to
indicate assertion of RSTI with DRESETEN negated caused the previous reset.
20.12.3 Software Watchdog Timer Reset Operation
A software watchdog timer is provided to allow periodic monitoring of software activity. If
the software watchdog is not periodically accessed by software it can programmed to
generate a reset after a timeout period. When the timeout occurs, an internal reset is asserted
for 32K clocks, resetting internal registers as with a normal reset. The RSTO pin
simultaneously asserts for 32K clocks after the software watchdog timeout. Figure 20-23
illustrates the timing of RSTO when asserted by a software watchdog timeout.
CLKIN
SOFTWARE
WATCHDOG
TIMEOUT
INTERNAL
RSTI
RSTO
BUS SIGNALS
Figure 20-23. Software Watchdog Timer Reset Timing
Chapter 20. Bus Operation
CLKIN CYCLES
T = 32K
Reset Operation
20-25