mcs7830 MosChip, mcs7830 Datasheet - Page 12

• Manufacturer Part Number: mcs7830
• Description: Usb-2.0 To Ethernet
• Manufacturer: MosChip

Page 12
MCS7830
USB-2.0 to Ethernet
Data Flow (USB to Ethernet MAC/PHY)
Endpoint-2 (Bulk-Out) is in charge of sending the
USB packets to Ethernet. An Ethernet packet is
concatenated from multiple USB packets (64 Bytes
in Full-Speed, and 512 Bytes in High-Speed). The
end of the Ethernet packet is indicated with either a
partial packet, or Zero-Length packets in this pipe.
The Ethernet transmit status is stored in the internal
FIFO of the Bridge. When the Bulk-Out endpoint is
accessed, if space is available in the internal SRAM of
the Bridge, data in the USB data stage is transferred
to SRAM and ACK is returned. If SRAM is not free,
then NAK is returned.
Dual-Port SRAM is used in this path (data fl ow from
USB to Ethernet MAC). The SRAM Controller stores
each individual USB packet (64 Bytes in Full Speed
and 512 Bytes in High Speed) in internal SRAM.
When the Endpoint Decoder signals End Of Packet,
a complete Ethernet packet is stored in SRAM. The
SRAM Controller then informs the Ethernet MAC to
transmit this packet. Approximately three Ethernet
packets of maximum size can be stored in SRAM.
If the SRAM is full, then the controller will inform the
Endpoint Decoder that SRAM is full, and the Endpoint
Decoder will return NAK, if accessing the Bulk-Out
endpoint is invoked. Thus additional USB packets
won’t be written into SRAM until it has free space.
Data Flow (Ethernet MAC/PHY to USB)
Endpoint-1 (Bulk-In) is in charge of sending received
Ethernet packets to the USB host. The Ethernet
packets received from the Ethernet MAC are stored
in the internal SRAM of the Bridge. If at least one
Ethernet frame is available in the SRAM, then the
Bridge informs readiness to the USB Device Controller
for transmission. If data is not ready in the SRAM for
transmission, then NAK is returned to the USB host.
An Ethernet packet will be split to multiple USB packets
(packet size is 64 Bytes in Full-Speed and 512 Bytes
in High-Speed). The end of the Ethernet packet is
indicated by a partial packet (less than 64 Bytes in
Full-Speed and less than 512 Bytes in High-Speed) or
a Zero-Length data transfer in this pipe. The Ethernet
received status is appended to the data as the last
Byte. While accessing this endpoint, if SRAM is full
or any packet is inside, the data in SRAM is returned
in the USB data stage. If ACK is received from the
USB host, the next packet available in the SRAM will
be transmitted in the next data stage. If no response
or NAK is received from the USB host, then the same
packet will be re-transmitted.
Received Ethernet packets are stored in the internal
Dual-Port SRAM. A total of fi ve Ethernet packets
of maximum size can be stored in SRAM. If more
than the maximum packet counts are received, then
the subsequent incoming Ethernet packets will be
discarded in the case of Half-Duplex mode. In the
case of Full-Duplex mode, the Ethernet MAC stops
receiving Ethernet packets from the PHY by using the
PAUSE frame mechanism.
The FIFO Controller will load data from SRAM into the
internal FIFO, and inform the USB Endpoint Decoder
that data is ready. Before the FIFO Controller does
this, any USB access to the Bulk-In endpoint will
return NAK. If an Ethernet packet is being received
and loaded into SRAM while the FIFO Controller is
moving data from SRAM to the FIFO, the SRAM bus is
shared by the controller for write and read operations
in alternate cycles.
Rev.
3.1