mcs1000 MosChip, mcs1000 Datasheet - Page 17

• Manufacturer Part Number: mcs1000
• Description: Security Processor
• Manufacturer: MosChip

Rev. 1.1
The operators have to start at the correct double-
word location. The HASH algorithm data is read-only
and is not written by the device. The operator blocks
must bypass the data and start at the correct location.
This is achieved by flushing the output buffers at the
beginning of the operation. This also guarantees the
correct block alignment. The DMA router and channel
arbiter control the flow of information inside the DMA
channel and serve two purposes:
This simplifies the operator architecture (There are
28 operators, but only one router for all of them) and
saves power by disconnecting the operator from the
chain in bypass mode. The disconnected operator
disconnects from the data transaction as opposed to
being simply in bypass mode. The disconnect has to
occur at the block aligned address for the operator,
otherwise an error is flagged by the DMA controller.
The IPSec Unit within the MCS1000 consists of
twenty-eight (28) blocks: four (4) Input channels, four
(4) Output channels, two (2) AES encryption blocks,
two (2) AES decryption blocks, four (4) DES/3DES
blocks, four (4) SHA-1 authentication blocks, four
(4) SHA-256 authentication blocks, and four (4) MD5
authentication blocks. The DMA channel performs the
arbitration between all 28 devices.
Configuration Access Interface
This unit sends the configuration data to the correct
operator or I/O channel. It generates the write pulses
that store the data into the configuration registers inside
the operator units. This unit converts VCI bus cycles
to operator configuration signals. The configuration
interface consists of 8 data transfer ports.
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Assemble the required operators into op
chains.
Control the start/end of the operator
processing inside the stream.
Input and Output Channel
These channels form the interface between the DMA
channel and the system memory. Memory transfers
are burst-oriented. It is possible to set the limit at which
the system memory transactions start. The channels
monitor the transfer count and hold it if it is less than a
full burst; once the count is full the data is transferred.
The maximum buffer size can be read from the channel
status word and the currently programmed buffer size
can be read from the channel control register. This
allows for tuning the burst sequence length to the
system memory.
protocol to connect to memory.
The data path consists of a FIFO and a Byte aligner.
The Byte aligner is always near the memory. In VCI
I/O operations, the memory data-path is twice as wide
as the DMA channel data-path. The data flows into the
input channel and out of the output channel. The Byte
aligner formats the double-word stream to be correctly
aligned in memory. For this the data is rotated and
multiplexed with the previous data depending on
the Byte start address. The FIFO is a double-word
asymmetric FIFO. The I/O channel DMA is the same
for both Input and Output channels. The difference
is in the start and end conditions. The configuration
register file is accessed via the configuration port
described above.
I/O channels use the basic VCI
MCS1000
Security Processor
Page 17