mcs1000 MosChip, mcs1000 Datasheet - Page 2

• Manufacturer Part Number: mcs1000
• Description: Security Processor
• Manufacturer: MosChip

Page 2
MCS1000
Security Processor
The Memory Controller can interface to standard
SDRAM and Flash memory. The SDRAM controller
supports up to 64 Mega Bytes of SDRAM. The non-
volatile memory controller can interface to 8-, 16- or
32-bit wide devices and has 26 address lines for up to
256 Mega Bytes of storage. The Memory Controller
has a Local Bus interface that supports 8-, 16- and
32-bit devices.
The PCI interface is a 32-bit 33MHz interface and it
complies with the PCI 2.0 standard. The internal PCI
controller acts as a slave device and can master the
bus, but it does not contain a PCI arbiter so it cannot
be a host PCI device in a system.
There are three (3) 10/100 Ethernet controllers
integrated into the MCS1000. Each controller consists
of an independent Media Access Controller (MAC) and
Physical Layer (PHY). The Ethernet interfaces can be
connected directly to external magnetics, LEDs and
connectors.
The General I/O interface has 16 bits of GPIO, a high-
speed UART and a JTAG interface. The GPIO is
controlled by the core processor and can be used for
any general bit manipulation and control.
The serial interface is typically configured to act as the
System Console, but it can also be used as a standard
RS-232 port supporting BAUD rates up to 115200
bps.
The JTAG port is reserved for test and debug only.
ARM is a registered trademark of ARM Limited.
All other brands or product names are the property of their respective holders.
Software and Operating System Support
The MCS1000 is based on an ARM926EJ-S
processor core, and supports any OS that will run
on this CPU platform. This processor core has a
Memory Management Unit (MMU) and supports
operating systems that require this unit in addition to
most popular OS’s / RTOS’s such as Windows-CE,
VxWorks from Wind River, Linux, etc.
MosChip Evaluation Board Configurations
MosChip has designed evaluation boards to
demonstrate both Stand-Alone and Peripheral Mode
configurations.
Rev.
1.1