ds4302 Maxim Integrated Products, Inc., ds4302 Datasheet - Page 6

• Manufacturer Part Number: ds4302
• Description: Ds4302 2-wire, 5-bit Dac With Three Digital Outputs
• Manufacturer: Maxim Integrated Products, Inc.

The DS4302 contains a 5-bit DAC and three programma-
ble digital outputs. The DAC setting and the pro-
grammed output levels are contained in a 1-byte data
word that defaults to 00h on power-up (see Figure 1 for
data byte configuration). The upper 5 MSbits of the byte
set the DAC and control the voltage produced on V
A setting of 1111 1XXX sets the minimum output voltage
from the DAC while a setting of 0000 0XXX sets the maxi-
mum output voltage from the DAC. The three LSbits of
the data byte control the three output pins, P0, P1, and
P2. Setting any of these control bits to a 0 pulls the corre-
sponding outputs low and setting the bits to a 1 pulls the
outputs high.
The DS4302 communicates through a 2-wire (SMBus-
compatible) digital interface and has a 2-wire address of
58h. Write and read operations are used to access the
DAC and output settings. Each operation begins with a
2-wire START condition, consists of three bytes, and
ends with a 2-wire STOP condition (see Figure 2). Using
the write operation, the 2-wire master can program the
2-Wire, 5-Bit DAC with Three Digital Outputs
Figure 1. Data Byte Configuration
Figure 2. 2-Wire Communication Examples
6
_____________________________________________________________________
COMMUNICATIONS KEY
WRITE A SINGLE BYTE
READ A SINGLE BYTE
X X X X X X X X
S
S
P
S
0 1 0
0
START
STOP
1
0
MSB
1
1
DAC VALUE
A
1 0 0
1
Detailed Description
58h
59h
0
ACK
DATA BYTE
0
8-BITS ADDRESS OR DATA
0
1
P2
A
A
P1
1
WHITE BOXES INDICATE THE MASTER IS
CONTROLLING SDA
SHADED BOXES INDICATE THE SLAVE IS
CONTROLLING SDA
0
P0
0
0
1
0
AAh
00h
0
0
1
0
0
0
1
0
OUT
0
0
.
A
A
5-bit DAC to adjust the voltage on VOUT and set the
level of the three output pins: P0, P1, and P2. The read
operation is used to recall the programmed settings.
The following terminology is commonly used to
describe 2-wire data transfers.
Master Device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses, START, and STOP conditions.
Slave Devices: Slave devices send and receive data
at the master’s request.
Bus Idle or Not Busy: Time between STOP and START
conditions when both SDA and SCL are inactive and in
their logic-high states. When the bus is idle, it initiates a
low-power mode for slave devices.
START Condition: A START condition is generated by
the master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a START condition. See Figure 3 for
applicable timing.
STOP Condition: A STOP condition is generated by the
master to end a data transfer with a slave. Transitioning
SDA from low to high while SCL remains high generates
a STOP condition. See Figure 3 for applicable timing.
Bit Write: Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
setup and hold time requirements (see Figure 3). Data is
shifted into the device during the rising edge of the SCL.
DATA BYTE
DATA BYTE
NOTES:
1) ALL BYTES ARE SENT MOST SIGNIFICANT BIT FIRST.
2) THE FIRST BYTE SENT AFTER A START CONDITION IS
A
ALWAYS THE SLAVE ADDRESS FOLLOWED BY THE
READ/WRITE BIT.
A
P
P
2-Wire Definitions