ltc2182 Linear Technology Corporation, ltc2182 Datasheet - Page 26

• Manufacturer Part Number: ltc2182
• Description: 16-bit, 65msps/ 40msps/25msps Low Power Dual Adcs
• Manufacturer: Linear Technology Corporation

APPLICATIONS INFORMATION
LTC2182/LTC2181/LTC2180
Digital Output Test Patterns
To allow in-circuit testing of the digital interface to the
A/D, there are several test modes that force the A/D data
outputs (OF , D15-D0) to known values:
The digital output test patterns are enabled by serially
programming mode control register A4. When enabled,
the Test Patterns override all other formatting modes: 2’s
complement, randomizer, alternate bit polarity.
Output Disable
The digital outputs may be disabled by serially program-
ming mode control register A3. All digital outputs including
OF and CLKOUT are disabled. The high-impedance disabled
state is intended for in-circuit testing or long periods of
inactivity – it is too slow to multiplex a data bus between
multiple converters at full speed. When the outputs are
disabled both channels should be put into either sleep or
nap mode.
Sleep and Nap Modes
The A/D may be placed in sleep or nap modes to conserve
power. In sleep mode the entire device is powered down,
resulting in 1mW power consumption. The amount of
time required to recover from sleep mode depends on the
size of the bypass capacitors on V
For the suggested values in Fig. 8, the A/D will stabilize
after 2ms.
In nap mode the A/D core is powered down while the internal
reference circuits stay active, allowing faster wakeup than
from sleep mode. Recovering from nap mode requires at
least 100 clock cycles. If the application demands very
accurate DC settling then an additional 50µs should be
26
All 1s: All outputs are 1
All 0s: All outputs are 0
Alternating: Outputs change from all 1s to all 0s on
alternating samples.
Checkerboard: Outputs change from
10101010101010101 to 01010101010101010 on
alternating samples.
REF
, REFH, and REFL.
allowed so the on-chip references can settle from the
slight temperature shift caused by the change in supply
current as the A/D leaves nap mode. Either channel 2 or
both channels can be placed in nap mode; it is not possible
to have channel 1 in nap mode and channel 2 operating
normally.
Sleep mode and nap mode are enabled by mode control
register A1 (serial programming mode), or by SDI and
SDO (parallel programming mode).
DEVICE PROGRAMMING MODES
The operating modes of the LTC2182/LTC2181/LTC2180
can be programmed by either a parallel interface or a
simple serial interface. The serial interface has more flex-
ibility and can program all available modes. The parallel
interface is more limited and can only program some of
the more commonly used modes.
Parallel Programming Mode
To use the parallel programming mode, PAR/SER should
be tied to V
logic inputs that set certain operating modes. These pins
can be tied to V
3.3V CMOS logic. When used as an input, SDO should
be driven through a 1k series resistor. Table 2 shows the
modes set by CS, SCK, SDI and SDO.
Table 2. Parallel Programming Mode Control Bits (PAR/SER = V
PIN
CS
SCK
SDI/SDO Power Down Control Bit
DESCRIPTION
Clock Duty Cycle Stabilizer Control Bit
Digital Output Mode Control Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
0 = Full-Rate CMOS Output Mode
1 = Double Data Rate LVDS Output Mode
00 = Normal Operation
01 = Channel 1 in Normal Operation, Channel 2 in Nap Mode
10 = Channel 1 and Channel 2 in Nap Mode
11 = Sleep Mode (Entire Device Powered Down)
DD
(3.5mA LVDS Current, Internal Termination Off)
. The CS, SCK, SDI and SDO pins are binary
DD
or ground, or driven by 1.8V, 2.5V, or
218210f
DD
)