ltc3851-1 Linear Technology Corporation, ltc3851-1 Datasheet - Page 21

• Manufacturer Part Number: ltc3851-1
• Description: Synchronous Step-down Switching Regulator Controller
• Manufacturer: Linear Technology Corporation

APPLICATIONS INFORMATION
4. Transition losses apply only to the topside MOSFET(s),
Other “hidden” losses such as copper trace and the bat-
tery internal resistance can account for an additional 5%
to 10% effi ciency degradation in portable systems. It is
very important to include these “system” level losses
during the design phase. The internal battery and fuse
resistance losses can be minimized by making sure that
C
switch ing frequency. A 25W supply will typically require a
minimum of 20μF to 40μF of capacitance having a maxi-
mum of 20mΩ to 50mΩ of ESR. Other losses including
Schottky conduction losses during dead time and induc-
tor core losses generally account for less than 2% total
additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V
amount equal to ΔI
series resistance of C
discharge C
forces the regulator to adapt to the current change and
return V
time V
ringing, which would indicate a stability problem. The
availability of the I
IN
DCR = 10mΩ and R
tance is 25mΩ. This results in losses ranging from 2%
to 8% as the output current increases from 3A to 15A
for a 5V output, or a 3% to 12% loss for a 3.3V output.
Effi ciency varies as the inverse square of V
same external components and output power level. The
combined effects of increasingly lower output voltages
and higher currents required by high performance digital
systems is not doubling but quadrupling the importance
of loss terms in the switching regulator system!
and become signifi cant only when operating at high
input voltages (typically 15V or greater). Transition
losses can be estimated from:
Transition Loss = (1.7)V
has adequate charge storage and very low ESR at the
OUT
OUT
can be monitored for excessive overshoot or
OUT
to its steady-state value. During this recovery
generating the feedback error signal that
TH
LOAD
OUT
pin not only allows optimization of
SENSE
(ESR), where ESR is the effective
. ΔI
IN
LOAD
2
= 5mΩ, then the total resis-
• I
O(MAX)
also begins to charge or
• C
OUT
RSS
shifts by an
OUT
• f
for the
control loop behavior but also provides a DC coupled and
AC fi ltered closed-loop response test point. The DC step,
rise time and settling at this test point truly refl ects the
closed-loop response. Assuming a predominantly second
order system, phase margin and/or damping factor can be
estimated using the percentage of overshoot seen at this
pin. The bandwidth can also be estimated by examining the
rise time at the pin. The I
in the Typical Application circuit will provide an adequate
starting point for most applications.
The I
loop compensation. The values can be modifi ed slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the fi nal PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80%
of full-load current having a rise time of 1μs to 10μs will
produce output voltage and I
give a sense of the overall loop stability without break ing
the feedback loop. Placing a power MOSFET directly
across the output capacitor and driving the gate with an
appropriate signal generator is a practical way to produce
a realistic load step condition. The initial output voltage
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This
is why it is better to look at the I
the feedback loop and is the fi ltered and compensated
control loop response. The midband gain of the loop will
be in creased by increasing R
loop will be increased by decreasing C
by the same factor that C
will be kept the same, thereby keeping the phase shift the
same in the most critical frequency range of the feedback
loop. The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance.
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
TH
OUT
series R
, causing a rapid drop in V
C
-C
C
fi lter sets the dominant pole-zero
C
TH
is decreased, the zero frequency
external components shown
C
TH
and the bandwidth of the
TH
pin waveforms that will
LTC3851-1
pin signal which is in
OUT
C
. If R
. No regulator can
C
is increased
21
38511f