ltc3862gn-1 Linear Technology Corporation, ltc3862gn-1 Datasheet - Page 13

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ltc3862gn-1

Manufacturer Part Number
ltc3862gn-1
Description
Multi-phase Current Mode Step-up Dc/dc Controller
Manufacturer
Linear Technology Corporation
Datasheet

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LTC3862GN-1
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In multi-phase applications, all of the FB pins are connected
together and all of the error amplifi er output pins (ITH) are
connected together. The INTV
be connected together. The INTV
sourcing current but is not capable of sinking current. As
a result, when two or more INTV
connected together, the highest voltage regulator supplies
all of the gate drive and control circuit current, and the
other regulators are off. This would place a thermal burden
on the highest output voltage LDO and could cause the
maximum die temperature to be exceeded. In multi-phase
LTC3862-1 applications, each INTV
should be independently bypassed to its respective PGND
pin as close as possible to each IC.
The Low Voltage Analog and Digital Supply LDO (3V8)
The second LDO within the LTC3862-1 is powered off
of INTV
analog and digital control circuitry, as shown in Figure 1.
The output voltage of this LDO (which also has a PMOS
output device) is 3.8V. Most of the analog and digital con-
trol circuitry is powered from the internal 3V8 LDO. The
3V8 pin should be bypassed to SGND with a 1nF ceramic
capacitor (X5R or better), placed as close as possible
to the IC pins. This LDO is not intended to be used as a
supply for external circuitry.
Thermal Considerations and Package Options
The LTC3862-1 is offered in three package options. The
5mm × 5mm QFN package (UH24) has a thermal resistance
R
thermal resistance of 38°C/W, and the 24-pin SSOP (GN24)
package has a thermal resistance of 85°C/W. The QFN and
TSSOP package options have a lead pitch of 0.65mm, and
the GN24 option has a lead pitch of 0.025in.
The INTV
current. As a result, care must be taken to ensure that
OPERATION
TH(JA)
of 34°C/W, the 24-pin TSSOP (FE24) package has a
CC
CC
and serves as the supply to the low voltage
regulator can supply up to 50mA of total
CC
pins, however, should not
CC
CC
regulator is capable of
regulator outputs are
CC
regulator output
the maximum junction temperature of the IC is never
exceeded. The junction temperature can be estimated
using the following equations:
The total quiescent current (I
supply current (I
the gate capacitance of the power MOSFETs. The value
of Q
Typical Performance Characteristics section of the MOSFET
data sheet. The value listed in the electrical specifi cations
may be measured at a higher V
value of interest is at the 10V INTV
As an example of the required thermal analysis, consider a
2-phase boost converter with a 8.5V to 24V input voltage
range and an output voltage of 72V at 1.5A. The switching
frequency is 150kHz and the maximum ambient tempera-
ture is 70°C. The power MOSFET used for this application
is the Renesas HAT2267H, which has a typical R
13mΩ at V
gate charge at V
fi cient of the gate charge is low). One power MOSFET is
used for each phase. For the QFN package option:
In this example, the junction temperature rise is only 9.8°C.
These equations demonstrate how the gate charge current
typically dominates the quiescent current of the IC, and
how the choice of package option and board heat sinking
can have a signifi cant effect on the thermal performance
of the solution.
I
P
T
I
P
T
Q(TOT)
Q(TOT)
J
J
DISS
DISS
G(TOT)
= T
= 70°C + 288mW • 34°C/W = 79.8°C
A
= V
= 24V • 12mA = 288mW
= I
= 3mA + 2 • 30nC • 150kHz = 12mA
+ P
should come from the plot of V
GS
IN
Q
DISS
= 10V. From the plot of V
+ Q
• (I
GS
Q
Q
G(TOT)
• R
) and the current required to charge
= 10V is 30nC (the temperature coef-
+ Q
TH(JA)
G(TOT)
• f
Q(TOT)
GS
• f)
, such as 15V, whereas the
) consists of the static
CC
LTC3862-1
gate drive voltage.
GS
vs Q
GS
vs Q
G
, the total
DS(ON)
13
G
in the
38621f
of

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