ltc3827ig-1 Linear Technology Corporation, ltc3827ig-1 Datasheet - Page 19

• Manufacturer Part Number: ltc3827ig-1
• Description: Low Iq, Dual, 2-phase Synchronous Step-down Controller
• Manufacturer: Linear Technology Corporation

APPLICATIO S I FOR ATIO
the input supply: V
boost capacitor C
input capacitance of the topside MOSFET(s). The reverse
breakdown of the external Schottky diode must be greater
than V
arbiter is the total input current for the regulator. If a
change is made and the input current decreases, then the
efficiency has improved. If there is no change in input
current, then there is no change in efficiency.
Fault Conditions: Current Limit and Current Foldback
The LTC3827-1 includes current foldback to help limit load
current when the output is shorted to ground. If the output
falls below 70% of its nominal output level, then the
maximum sense voltage is progressively lowered from
100mV to 30mV. Under short-circuit conditions with very
low duty cycles, the LTC3827-1 will begin cycle skipping
in order to limit the short-circuit current. In this situation
the bottom MOSFET will be dissipating most of the power
but less than in normal operation. The short-circuit ripple
current is determined by the minimum on-time t
of the LTC3827-1 (≈180ns), the input voltage and in-
ductor value:
The resulting short-circuit current is:
Fault Conditions: Overvoltage Protection (Crowbar)
The overvoltage crowbar is designed to blow a system
input fuse when the output voltage of the regulator rises
much higher than nominal levels. The crowbar causes
huge currents to flow, that blow the fuse to protect against
a shorted top MOSFET if the short occurs while the
controller is operating.
A comparator monitors the output for overvoltage condi-
tions. The comparator (OV) detects overvoltage faults
greater than 10% above the nominal output voltage. When
this condition is sensed, the top MOSFET is turned off and
the bottom MOSFET is turned on until the overvoltage
condition is cleared. The bottom MOSFET remains on
continuously for as long as the OV condition persists; if
ΔI
I
SC
L(SC)
IN(MAX)
=
R
30
= t
SENSE
mV
ON(MIN)
. When adjusting the gate drive level, the final
B
–
BOOST
needs to be 100 times that of the total
U
2
1
(V
Δ
IN
I
L SC
= V
/L)
(
U
IN
)
+ V
INTVCC
W
. The value of the
U
ON(MIN)
V
cally resumes. A shorted top MOSFET will result in a high
current condition which will open the system fuse. The
switching regulator will regulate properly with a leaky
top MOSFET by altering the duty cycle to accommodate
the leakage.
Phase-Locked Loop and Frequency Synchronization
The LTC3827-1 has a phase-locked loop (PLL) comprised
of an internal voltage-controlled oscillator (VCO) and a
phase detector. This allows the turn-on of the top MOS-
FET of controller 1 to be locked to the rising edge of an
external clock signal applied to the PLLIN/MODE pin. The
turn-on of controller 2’s top MOSFET is thus 180 degrees
out of phase with the external clock. The phase detector
is an edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
The output of the phase detector is a pair of complemen-
tary current sources that charge or discharge the external
filter network connected to the PLLLPF pin. The relation-
ship between the voltage on the PLLLPF pin and operating
frequency, when there is a clock signal applied to PLLIN/
MODE, is shown in Figure 9 and specified in the Electrical
Characteristics table. Note that the LTC3827-1 can only be
synchronized to an external clock whose frequency is
within range of the LTC3827-1’s internal VCO, which is
nominally 115kHz to 800kHz. This is guaranteed to be
between 140kHz and 650kHz. A simplified block diagram
is shown in Figure 10.
If the external clock frequency is greater than the internal
oscillator’s frequency, f
tinuously from the phase detector output, pulling up the
PLLLPF pin. When the external clock frequency is less
than f
PLLLPF pin. If the external and internal frequencies are the
same but exhibit a phase difference, the current sources
turn on for an amount of time corresponding to the phase
difference. The voltage on the PLLLPF pin is adjusted until
the phase and frequency of the internal and external
oscillators are identical. At the stable operating point, the
phase detector output is high impedance and the filter
capacitor C
OUT
returns to a safe level, normal operation automati-
OSC
, current is sunk continuously, pulling down the
LP
holds the voltage.
OSC
, then current is sourced con-
LTC3827-1
19
38271fd