ltc3890-1 Linear Technology Corporation, ltc3890-1 Datasheet - Page 27

• Manufacturer Part Number: ltc3890-1
• Description: 60v Low Iq, Dual, 2-phase Synchronous Step-down Dc/dc Controller
• Manufacturer: Linear Technology Corporation

APPLICATIONS INFORMATION
3. Do the LTC3890-1 V
4. Are the SENSE
5. Is the INTV
6. Keep the switching nodes (SW1, SW2), top gate nodes
7. Use a modifi ed star ground technique: a low impedance,
leads and PC trace lengths. The output capacitor (–)
terminals should be connected as close as possible
to the (–) terminals of the input capacitor by placing
the capacitors next to each other and away from the
Schottky loop described above.
the (+) terminals of C
connected between the (+) terminal of C
ground. The feedback resistor connections should not
be along the high current input feeds from the input
capacitor(s).
with minimum PC trace spacing? The fi lter capacitor
between SENSE
possible to the IC. Ensure accurate current sensing with
Kelvin connections at the SENSE resistor.
to the IC, between the INTV
pins? This capacitor carries the MOSFET drivers’ cur-
rent peaks. An additional 1μF ceramic capacitor placed
immediately next to the INTV
help improve noise performance substantially.
(TG1, TG2), and boost nodes (BOOST1, BOOST2) away
from sensitive small-signal nodes, especially from
the opposites channel’s voltage and current sensing
feedback pins. All of these nodes have very large and
fast moving signals and therefore should be kept on
the output side of the LTC3890-1 and occupy minimum
PC trace area.
large copper area central grounding point on the same
side of the PC board as the input and output capacitors
with tie-ins for the bottom of the INTV
capacitor, the bottom of the voltage feedback resistive
divider and the SGND pin of the IC.
CC
decoupling capacitor connected close
–
+
and SENSE
and SENSE
FB
OUT
pins’ resistive dividers connect to
? The resistive divider must be
CC
+
–
CC
should be as close as
and the power ground
leads routed together
and PGND pins can
OUT
CC
decoupling
and signal
PC Board Layout Debugging
Start with one controller on at a time. It is helpful to use
a DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope to
the internal oscillator and probe the actual output voltage
as well. Check for proper performance over the operating
voltage and current range expected in the application. The
frequency of operation should be maintained over the input
voltage range down to dropout and until the output load
drops below the low current operation threshold—typi-
cally 15% of the maximum designed current level in Burst
Mode operation.
The duty cycle percentage should be maintained from cycle
to cycle in a well-designed, low noise PCB implementation.
Variation in the duty cycle at a subharmonic rate can sug-
gest noise pickup at the current or voltage sensing inputs
or inadequate loop compensation. Overcompensation of
the loop can be used to tame a poor PC layout if regula-
tor bandwidth optimization is not required. Only after
each controller is checked for its individual performance
should both controllers be turned on at the same time.
A particularly diffi cult region of operation is when one
controller channel is nearing its current comparator trip
point when the other channel is turning on its top MOSFET.
This occurs around 50% duty cycle on either channel due
to the phasing of the internal clocks and may cause minor
duty cycle jitter.
Reduce V
of the regulator in dropout. Check the operation of the
undervoltage lockout circuit by further lowering V
monitoring the outputs to verify operation.
Investigate whether any problems exist only at higher out-
put currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
IN
from its nominal level to verify operation
LTC3890-1
IN
27
while
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