ltc4268cdkd-1-trpbf Linear Technology Corporation, ltc4268cdkd-1-trpbf Datasheet - Page 16
![no-image](/images/manufacturer_photos/0/3/389/linear_technology_corporation_sml.jpg)
ltc4268cdkd-1-trpbf
Manufacturer Part Number
ltc4268cdkd-1-trpbf
Description
High Power Pd With Synchronous Noopto Flyback Controller
Manufacturer
Linear Technology Corporation
Datasheet
1.LTC4268CDKD-1-TRPBF.pdf
(48 pages)
- Current page: 16 of 48
- Download datasheet (414Kb)
APPLICATIONS INFORMATION
The IEEE 802.3af specifi cation requires the PSE to use
a ΔV/ΔI measurement technique to keep the DC offset
voltage of the diode bridge from affecting the signature
resistance measurement. However, the diode resistance
appears in series with the signature resistor and must be
included in the overall signature resistance of the PD.
LTC4268-1
16
Figure 3. V
IN
Voltage, PWRGD, PWRGD and PD Current as a Function of Port Voltage
PSE
V
PORT
I
I
LIMIT_HIGH
LIMIT_LOW
R
CLASS
I
I
IN
CLASS
I
I
I
I
CLASS
LIMIT_LOW
1
LOAD
–10
–20
–30
–40
–50
–10
–20
–30
–40
–50
–10
–20
–30
–40
–50
20
10
=
V1 – 2 DIODE DROPS
=
DEPENDENT ON R
R
R
V
V
LOAD
dV
CLASS
PORTN
dt
= 300mA, I
IN
UVLO
LTC4268-1
OFF
25kΩ
=
I
POWER
POWER
DETECTION V1
LIMIT_LOW
BAD
BAD
DETECTION V2
DETECTION I
DETECTION I
CLASSIFICATION
PWRGD
PWRGD
V
C1
CLASSIFICATION
PORTP
V
LIMIT_HIGH
NEG
UVLO
TURN-ON
The LTC4268-1 compensates for the two series diodes in
the signature path by offsetting the internal resistance so
that a PD built with the LTC4268-1 meets the IEEE 802.3af
specifi cation.
CLASS
UVLO
ON
POWER
POWER
I
GOOD
GOOD
2
1
2
=
SELECTION
= 750mA
V2 – 2 DIODE DROPS
+
PWRGD TRACKS
V
UVLO
TURN-OFF
POWER
IN
25kΩ
LOAD, I
(UP TO I
BAD
= R
POWER
R
UVLO
LOAD
OFF
BAD
C1
LOAD
TIME
TIME
TIME
TIME
TIME
LOAD
LIMIT_HIGH
C1
42681 F03
V
IN
)
42681fa
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