ltc6416 Linear Technology Corporation, ltc6416 Datasheet - Page 11

• Manufacturer Part Number: ltc6416
• Description: 2 Ghz Low Noise Differential 16-bit Adc Buffer
• Manufacturer: Linear Technology Corporation

PIN FUNCTIONS
V
seen at OUT
internal buffer with a high output resistance of 6k. The V
pin has a Thevenin equivalent resistance of approximately
3.8k and can be overdriven by an external voltage. If no
voltage is applied to V
of approximately 1.25V on a 3.3V supply or 1.36V on
a 3.6V supply. The V
high-quality ceramic bypass capacitor of at least 0.1μF .
CLHI (Pin 2): High Side Clamp Voltage. The voltage applied
to the CLHI pin defi nes the upper voltage limit of the OUT
and OUT
above the upper voltage range of the driven ADC. On a 3.3V
supply, the CLHI pin will fl oat to a 2.23V default voltage.
On a 3.6V supply, the CLHI pin will fl oat to a 2.45V default
voltage. CLHI has a Thevenin equivalent of approximately
4.1kΩ and can be overdriven by an external voltage. The
CLHI pin should be bypassed with a high-quality ceramic
bypass capacitor of at least 0.1μF .
IN
of the buffer, respectively. These pins are high impedance,
approximately 6kΩ. If AC-coupled, these pins will self bias
to the voltage present at the V
CLLO (Pin 5): Low Side Clamp Voltage. The voltage ap-
plied to the CLLO pin defi nes the lower voltage limit of
the OUT
least 300mV below the lower voltage range of the driven
DC TEST CIRCUIT SCHEMATIC
CM
+
,IN
(Pin 1): This pin sets the output common mode voltage
–
(Pins 3, 4): Non-inverting and inverting input pins
+
–
pins. This voltage should be set at least 300mV
and OUT
+
and OUT
V
V
–
INDIFF
INCM
pins. This voltage should be set at
CM
–
CM
=
by driving IN
= IN
IN
, it will fl oat to a default voltage
pin should be bypassed with a
+
+
+ IN
2
– IN
–
–
CM
IN
IN
pin.
+
–
CLLO
CLHI
V
CM
+
and IN
1
2
3
4
5
V
CLHI
CLLO
IN
IN
V
V
CM
+
+
+
–
10
6
–
LTC6416
through an
9
11
OUT
OUT
+
–
CM
8
7
+
ADC. On a 3.3V supply, the CLLO pin will fl oat to a 0.25V
default voltage. On a 3.6V supply, the CLLO pin will fl oat to
a 0.265V default voltage. CLLO has a Thevenin equivalent
resistance of approximately 2.3k and can be overdriven by
an external voltage. The CLLO pin should be bypassed with
a high quality ceramic bypass capacitor of at least 0.1μF .
GND (Pins 6, 9, 11): Negative power supply, normally
tied to ground. Both pins and the exposed paddle must
be tied to the same voltage. GND may be tied to a voltage
other than ground as long as the voltage between V
GND is 2.7V to 4V. If the GND pins are not tied to ground,
bypass them with 680pF and 0.1μF capacitors as close to
the package as possible.
OUT
are low impedance. Each output has an output impedance
of approximately 9Ω at DC.
V
Split supplies are possible as long as the voltage between
V
and 0.1μF as close to the part as possible should be used
between the supplies.
Exposed Pad (Pin 11): Ground. The exposed pad must
be soldered to the printed circuit board ground plane for
good heat transfer. If GND is a voltage other than ground,
the Exposed Pad must be connected to a plane with the
same potential as the GND pins – Not to the system
ground plane.
+
+
C
(Pin 10): Positive Power Supply. Typically 3.3V to 3.6V.
and GND is 2.7V to 4V. Bypass capacitors of 680pF
LOAD
–
, OUT
R
LOAD
+
6416 DC
(Pins 7, 8): Outputs. The LTC6416 outputs
OUT
OUT
–
+
V
V
OUTDIFF
OUTCM
=
= OUT
OUT
+
+
+ OUT
2
– OUT
–
–
LTC6416
11
+
and
6416f