sg2567udr212851hc ETC-unknow, sg2567udr212851hc Datasheet - Page 20

• Manufacturer Part Number: sg2567udr212851hc
• Description: Dram Module Ddr2 Sdram 2gbyte 240udimm
• Manufacturer: ETC-unknow

IDD Specification Parameters and Test Conditions
(V
Corporate Headquarters: P. O. Box 1757, Fremont, CA 94538, USA • Tel:[phone] • Fax:[phone] • E-mail: [e-mail]
Europe: 5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: [phone] • Fax: [phone]
Asia/Pacific: Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: [phone] • Fax: [phone]
Symbol
IDD0
IDD1
IDD2P
IDD2Q
IDD2N
IDD3P
IDD3N
IDD4W
IDD4R
IDD5B
IDD6
IDD7
DD
= 1.8V±0.1V, V
Parameter
Operating one bank active–precharge current; t
CKE and CS# are HIGH between valid commands; Address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
Operating one bank active–read–precharge current; I
t
between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W
Precharge power–down current; All banks idle; t
address bus inputs are STABLE; Data bus inputs are FLOATING
Precharge quiet standby current; All banks idle; t
control and address bus inputs are STABLE; Data bus inputs are FLOATING
Precharge standby current; All banks idle; t
and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Active power–down current; All banks open; t
Other control and address bus inputs are STABLE; Data bus inputs are FLOAT-
ING
Active standby current; All banks open; t
HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL =
0; t
mands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst read current; All banks open, Continuous burst reads, I
CL(IDD), AL = 0; t
between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W
Burst refresh current; t
CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data
bus inputs are SWITCHING
Self refresh current; CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus inputs are
FLOATING; Data bus inputs are FLOATING
Operating bank interleave read current; All bank interleaving reads, I
CL(IDD), AL = t
1*t
during DESELECTs; Data pattern is same as IDD4R
CK
CK(IDD)
CK
= t
= t
CK(IDD),
CK(IDD),
; CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are STABLE
SS
t
RCD(IDD)
RC
t
CK
RAS
= 0V, T
= t
= t
RC(IDD),
= t
CK(IDD),
CK
-1*t
RASmax(IDD),
= t
CK(IDD)
A
CK(IDD)
t
= 0 to +65°C)
RAS
t
RAS
; t
= t
CK
; Refresh command at every t
= t
RASmin(IDD),
t
RP
RASmax(IDD),
= t
CK
= t
CK(IDD),
CK
= t
RP(IDD)
CK
CK(IDD),
= t
CK
CK
CK(IDD);
CK
= t
t
t
RC
RCD
= t
CK(IDD);
; CKE is HIGH, CS# is HIGH between valid com-
= t
= t
t
RP
CK(IDD),
CK(IDD);
OUT
= t
t
CK(IDD);
RAS
= t
= t
RC(IDD),
CKE is HIGH, CS# is HIGH; Other control
RCD(IDD)
RP(IDD)
= 0mA; BL = 4, CL = CL(IDD), AL = 0;
= t
CKE is LOW;
RASmax(IDD),
t
CKE is LOW; Other control and
RC
CKE is HIGH, CS# is HIGH; Other
RFC(IDD)
t
RRD
= t
; CKE is HIGH, CS# is HIGH
; CKE and CS# are HIGH
OUT
RC(IDD),
OUT
= t
SG2567UDR212851UU
= 0mA; BL = 4, CL =
RRD(IDD),
interval; CKE is HIGH,
= 0mA; BL = 4, CL =
t
RP
t
RAS
Fast PDN Exit
MRS(12) = 0
Slow PDN Exit
MRS(12) = 1
= t
RP(IDD)
= t
t
RCD
RASmin(IDD)
=
; CKE is
;
March 17, 2008
CL 5.0
2.5ns
1350
1530
1080
1980
1980
2655
3555
126
900
900
900
630
126
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
20