fw802a ETC-unknow, fw802a Datasheet
fw802a
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fw802a Summary of contents
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... FW802A Low-Power PHY IEEE* 1394A-2000 Two-Cable Transceiver/Arbiter Device Distinguishing Features Compliant with IEEE Standard 1394a-2000, IEEE I Standard for a High Performance Serial Bus Amendment 1. Low-power consumption during powerdown or I microlow-power sleep mode. Supports extended BIAS_HANDSHAKE time for I enhanced interoperability with camcorders. While unpowered and connected to the bus, will not ...
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Two-Cable Transceiver/Arbiter Device Contents Distinguishing Features ......................................................................................................................................... 1 Features ................................................................................................................................................................ 1 Other Features ...................................................................................................................................................... 1 Description ............................................................................................................................................................. 3 Signal Information .................................................................................................................................................. 6 Application Information ........................................................................................................................................ 10 Crystal Selection Considerations ......................................................................................................................... 11 1394 Application Support Contact Information .................................................................................................... 12 Absolute Maximum ...
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... IEEE 1394-1995 Annex J. To operate with bus-keeper isolation, the /ISO pin of the FW802A must be tied high. Data bits to be transmitted through the cable ports are received from the LLC on two, four, or eight data lines (D[0:7]), and are latched internally in the PHY in synchronization with the 49 ...
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... For those applications, when FW802A is used with one of the ports not brought out to a connector, those unused ports may be left unconnected without normal termination. When a port ...
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... The SYSCLK output will become active (and the PHY/ link interface will be initialized and become operative) within 3 ms after LPS is asserted high, when the FW802A is in the low-power mode. CPS LPS /ISO CNA ...
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... CNA 15 LPS 16 Note: Active-low signals are indicated by “/” at the beginning of signal names, within this document PIN #1 IDENTIFIER AGERE FW802A Figure 2. Pin Assignments June 2001 DDA 42 TPBIAS1 41 TPA1+ 40 TPA1– ...
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... After hardware reset, this pin is set as an output. If the LPS is inactive, C/LKON indicates one of the following events by asserting a 6.114 MHz signal. 1. FW802A receives a link-on packet addressed to this node. 2. Port_event register bit Any of the Timeout, Pwr_Fail, or Loop register bits are 1 and the Resume_int register bit is also 1 ...
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... V Powerdown. When asserted high, PD turns off all internal circuitry except the bias-detect circuits that drive the CNA signal. Internal FW802A logic is kept in the reset state as long asserted. PD terminal is provided for backward compatibility recommended that the FW802A be allowed to manage its own power consumption using suspend/resume in conjunction with LPS ...
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June 2001 Signal Information (continued) Table 1. Signal Descriptions (continued) Pin Signal* Type 35 TPA0− Analog I/O Portn, Port Cable Pair A. TPAn is the port A connection to the twisted- 40 TPA1− 34 TPB0+ Analog I/O Portn, Port Cable ...
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... CNA 15 LPS LLC PULSE See Figure 4 for typical port termination network. Figure 3. Typical External Component Connections PIN #1 IDENTIFIER AGERE FW802A June 2001 DDA 43 TPBIAS1 42 TPA1+ 41 TPA1– PORT 1* ...
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... E-mail: 1394support@agere.com Crystal Selection Considerations The FW802A is designed to use an external 24.576 MHz crystal connected between the XI and XO terminals to provide the reference for an internal oscillator circuit. IEEE 1394a-2000 standard requires that FW802A have less than ±100 ppm total variation from the nominal data rate, which is directly influenced by the crystal. To achieve this recommended that an oscillator with a nominal 50 ppm or less frequency tolerance be used. The total frequency variation must be kept below ± ...
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... The layout of the crystal portion of the PHY circuit is important for obtaining the correct frequency and minimizing noise introduced into the FW802A PLL. The crystal and two load capacitors should be considered as a unit during layout. They should be placed as close as possible to one another, while minimizing the loop area created by the combination of the three components ...
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June 2001 Electrical Characteristics Table 3. Analog Characteristics Parameter Supply Voltage Differential Input Voltage Cable inputs, 100 Mbits/s operation Cable inputs, 200 Mbits/s operation Cable inputs, 400 Mbits/s operation Cable inputs, during arbitration Common-mode Voltage Source Power Mode Common-mode Voltage ...
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Two-Cable Transceiver/Arbiter Device Electrical Characteristics Table 4. Driver Characteristics Parameter Differential Output Voltage Off-state Common-mode Voltage Driver Differential Current, TPA+, TPA−, TPB+, TPB− Common-mode Speed Signaling Current, TPB+, TPB− * Limits are defined as the algebraic sum of TPA+ and ...
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June 2001 Electrical Characteristics Table 5. Device Characteristics Parameter Supply Current: One Port Active All Ports Active Microlow-Power Sleep Mode High-level Output Voltage Low-level Output Voltage High-level Input Voltage Low-level Input Voltage Pull-up Current, /RESET Input Powerup ...
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Two-Cable Transceiver/Arbiter Device Timing Characteristics Table 6. Switching Characteristics Symbol Parameter — Jitter, Transmit — Transmit Skew t Rise Time, Transmit (TPA/TPB Fall Time, Transmit (TPA/TPB Setup Time, su Dn, CTLn, LREQ↑↓ to SYSCLK↑ t Hold ...
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June 2001 Timing Waveforms Figure 5. Dn, CTLn, and LREQ Input Setup and Hold Times Waveforms Figure 6. Dn, CTLn Output Delay Relative to SYSCLK Waveforms Agere Systems Inc. Two-Cable Transceiver/Arbiter Device SYSCLK tsu Dn, CTLn, LREQ SYSCLK td Dn, ...
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Two-Cable Transceiver/Arbiter Device Internal Register Configuration The PHY register map is shown below in Table 8. Table 8. PHY Register Map for the Cable Environment Address Bit 0 Bit 1 0000 2 0001 RHB IBR 2 0010 Extended (7) 2 ...
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June 2001 Internal Register Configuration Table 9. PHY Register Fields for the Cable Environment (continued) Field Size Type Power Reset Value Total_ports 4 r Max_speed 3 r Delay 4 r LCtrl 1 rw Contender 1 rw See description. Jitter 3 ...
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Two-Cable Transceiver/Arbiter Device Internal Register Configuration Table 9. PHY Register Fields for the Cable Environment (continued) Field Size Type Power Reset Enab_accel 1 rw Enab_multi 1 rw Page_select 3 rw Port_select 4 rw The port status page is used to ...
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June 2001 Internal Register Configuration The meaning of the register fields with the port status page are defined by Table 11 below. Table 11. PHY Register Port Status Page Fields Field Size Type AStat 2 r BStat 2 r Child ...
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... Table 13. PHY Register Vendor Identification Page Fields Field Size Type Compliance_level 8 r Vendor_ID 24 r Product_ID 24 r The vendor-dependent page provides access to information used in manufacturing test of the FW802A (continued) . The format of the vendor identification page is 2 Contents Bit 2 Bit 3 Bit 4 Compliance_level Vendor_ID ...
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... Outline Diagrams 64-Pin TQFP Dimensions are in millimeters . 12.00 ± 0.20 10.00 ± 0.20 PIN #1 IDENTIFIER ZONE DETAIL A DETAIL B 0.50 TYP Ordering Information Device Code Package FW802A-DB 64-Pin TQFP Agere Systems Inc. Two-Cable Transceiver/Arbiter Device 49 48 10.00 ± 0.20 12.00 ± 0. 1.40 ± 0.05 1.60 MAX SEATING PLANE 0.08 0.05/0.15 Comcode 108698549 1 ...
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For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@micro.lucent.com N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Agere ...