fw802a ETC-unknow, fw802a Datasheet - Page 5

• Manufacturer Part Number: fw802a
• Description: Low-power Ieee 1394a-2000 Two-cable Transceiver/arbiter Device
• Manufacturer: ETC-unknow

June 2001
Description
to become active in order to respond to the event or to
notify the LLC of the event (e.g., incoming bias or dis-
connection is detected on a suspended port, a new
connection is detected on a nondisabled port, etc.).
The SYSCLK output will become active (and the PHY/
link interface will be initialized and become operative)
within 3 ms after LPS is asserted high, when the
FW802A is in the low-power mode.
Agere Systems Inc.
SYSCLK
C/LKON
/RESET
LREQ
CTL0
CTL1
CNA
CPS
/ISO
PC0
PC1
PC2
LPS
SM
PD
SE
D0
D1
D2
D3
D4
D5
D6
D7
(continued)
INTERFACE
LINK
I/O
Figure 1. Block Diagram
ARBITRATION
RECEIVED
DECODER/
TRANSMIT
ENCODER
RETIMER
CONTROL
MACHINE
DATA
STATE
DATA
LOGIC
AND
Two of the signals are used to set up various test
conditions used in manufacturing. These signals (SE
and SM) should be connected to V
operation.
Two-Cable Transceiver/Arbiter Device
CABLE PORT 0
CABLE PORT 1
OSCILLATOR,
PLL SYSTEM,
GENERATOR
GENERATOR
CURRENT
VOLTAGE
CRYSTAL
CLOCK
BIAS
AND
AND
SS
TPA0+
TPA0–
TPB0+
TPB0–
TPA1+
TPA1–
TPB1+
TPB1–
XI
XO
R0
R1
TPBIAS0
TPBIAS1
for normal
5-5459.f (F)
5