cy7c1380b-200bzc Cypress Semiconductor Corporation., cy7c1380b-200bzc Datasheet - Page 6

• Manufacturer Part Number: cy7c1380b-200bzc
• Description: 512k X 36/1m X 18 Pipelined Sram
• Manufacturer: Cypress Semiconductor Corporation.

Pin Definitions
Document #: 38-05267 Rev. *A
A0
A1
A
BWa
BWb
BWc
BWd
GW
BWE
CLK
CE
CE
CE
OE
ADV
ADSP
ADSC
MODE
ZZ
DQa, DPa
DQb, DPb
DQc, DPc
DQd, DPd
TDO
1
2
3
Name
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-Clock
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input Pin
Input-
Asynchronous
I/O-
Synchronous
JTAG serial output
Synchronous
I/O
Address Inputs used to select one of the address locations. Sampled at the
rising edge of the CLK if ADSP or ADSC is active LOW, and CE
CE
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte
writes to the SRAM. Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW. When asserted LOW on the rising
edge of CLK, a global write is conducted (ALL bytes are written, regardless of
the values on BW
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This
signal must be asserted LOW to conduct a byte write.
Clock Input. Used to capture all synchronous inputs to the device. Also used
to increment the burst counter when ADV is asserted LOW, during a burst
operation.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used
in conjunction with CE
nored if CE
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used
in conjunction with CE
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used
in conjunction with CE
Output Enable, asynchronous input, active LOW. Controls the direction of the
I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH,
I/O pins are three-stated, and act as input data pins. OE is masked during the
first clock of a read cycle when emerging from a deselected state.
Advance Input signal, sampled on the rising edge of CLK. When asserted, it
automatically increments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK. When
asserted LOW, A is captured in the address registers. A
into the burst counter. When ADSP and ADSC are both asserted, only ADSP
is recognized. ASDP is ignored when CE
Address Strobe from Controller, sampled on the rising edge of CLK. When
asserted LOW, A
into the burst counter. When ADSP and ADSC are both asserted, only ADSP
is recognized.
Selects Burst Order. When tied to GND selects linear burst sequence. When
tied to V
pin and should remain static during device operation.
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical
“sleep” condition with data integrity preserved.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register
that is triggered by the rising edge of CLK. As outputs, they deliver the data
contained in the memory location specified by A
rise of the read cycle. The direction of the pins is controlled by OE. When OE
is asserted LOW, the pins behave as outputs. When HIGH, DQx and DPx are
placed in a three-state condition.DQ a,b,c and d are 8 bits wide. DP a,b,c and
d are 1 bit wide.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
(BGA Only)
3
are sampled active. A
DDQ
1
or left floating selects interleaved burst sequence. This is a strap
is HIGH.
[x:0]
a,b,c,d
is captured in the address registers. A
2
1
1
and BWE).
and CE
and CE
and CE
[1:0]
feed the 2-bit counter.
2
3
3
Description
to select/deselect the device.(TQFP Only)
to select/deselect the device. ADSP is ig-
to select/deselect the device.(TQFP Only)
1
is deasserted HIGH.
X
during the previous clock
CY7C1380B
CY7C1382B
[1:0]
[1:0]
are also loaded
are also loaded
1,
Page 6 of 34
CE
2
, and