CY7C138-25JC Cypress Semiconductor Corp, CY7C138-25JC Datasheet
CY7C138-25JC
Specifications of CY7C138-25JC
Available stocks
Related parts for CY7C138-25JC
CY7C138-25JC Summary of contents
Page 1
... Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a chip enable (CE) pin or SEM pin. The CY7C138 and CY7C139 are available in a 68-pin PLCC. I/O I/O CONTROL ...
Page 2
... Interrupt Flag. INT is set when right port writes location FFE and is cleared L when left port reads location FFE. INT FFF and is cleared when right port reads location FFF. Busy Flag Master or Slave Select Power Ground 7C138-15 7C139-15 15 220 60 2 CY7C138 CY7C139 ...
Page 3
... Ind V > V – 0. < 0.2V, Active IN [6] Port Outputs MAX (except output enable means no address or control lines change. This applies only to inputs at CMOS 3 CY7C138 CY7C139 Ambient Temperature + ± 10% – + ± 10% 7C138-15 7C138-25 7C139-15 7C139-25 Min. Max. Min. Max. Unit 2 ...
Page 4
... MAX Test Conditions MHz 5. =250 TH OUTPUT C=30pF V TH (b) Thé venin Equivalent ( Load 1) ALL INPUT PULSES 3.0V 90% 90% 10% GND < CY7C138 CY7C139 7C138-35 7C138-55 7C139-35 7C139-55 Min. Max. Min. Max. 2.4 2.4 0.4 0.4 2.2 2.2 0.8 0.8 –10 +10 –10 +10 –10 +10 –10 ...
Page 5
... R/W HIGH after BUSY HIGH WH [14] t BUSY HIGH to Data Valid BDD [13] INTERRUPT TIMING t INT Set Time INS t INT Reset Time INR [8] 7C138-15 7C138-25 7C138-35 7C139-15 7C139-25 7C139-35 Min. Max. Min. Max. Min Note Note CY7C138 CY7C139 7C138-55 7C139-55 Max. Min. Max. Unit Note Note ...
Page 6
... Min [15, 16 [15, 17, 18] t ACE t DOE t LZOE is less than t and t HZCE LZCE - t (actual (actual). WDD PWE DDD SD 6 CY7C138 CY7C139 7C138-35 7C138-55 7C139-35 7C139-55 Max. Min. Max. Min. Max DATA VALID t HZCE t HZOE DATA VALID less than t . HZOE LZOE Unit ns ns ...
Page 7
... R/W must be HIGH during all address transitions. [19, 20 MATCH t PWE MATCH t WDD [21, 22, 23 SCE PWE t t HZOE HIGH IMPEDANCE or (t PWE HZWE 7 CY7C138 CY7C139 VALID t DDD VALID DATA VALID t LZOE + allow the I/O drivers to turn off and data to be placed on the SD C138-10 C138-11 ...
Page 8
... CE = HIGH for the duration of the above timing (both write and read cycle). [21, 23, 24 SCE PWE HZWE [25 SCE SOP t SD DATA VALID PWE t SWRD t SOP WRITE CYCLE READ CYCLE 8 CY7C138 CY7C139 DATA VALID t LZWE HIGH IMPEDANCE C138-12 t OHA VALID ADDRESS t ACE DATA VALID OUT t DOE C138-13 ...
Page 9
... SPS [26, 27, 28] MATCH t SPS MATCH [20 MATCH t PWE t SD VALID MATCH t BLA t WDD t PWE HIGH L 9 CY7C138 CY7C139 C138- BHA t BDD t DDD VALID C138-15 C138-16 ...
Page 10
... BUSY will be asserted. PS [29] ADDRESS MATCH BLC ADDRESS MATCH BLC [29 ADDRESS MISMATCH t t BLA BHA ADDRESS MISMATCH t t BLA BHA 10 CY7C138 CY7C139 t BHC C138-17 t BHC C138-18 C138-19 C138-20 ...
Page 11
... R 31 depends on which enable pin (CE or R/W INS INR WRITE FFF t [30] HA [31] [31] t INR t WC WRITE FFE t [30] HA [31] [31] t INR ) is deasserted first asserted last CY7C138 CY7C139 C138- READ FFF C138-22 C138- READ FFE C138-24 ...
Page 12
... Architecture The CY7C138/9 consists of an array of 4K words of 8/9 bits each of dual–port RAM cells, I/O and address lines, and con- trol signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simul- taneous writes/reads to the same location, a BUSY pin is provided on each port. Two interrupt (INT) pins can be utilized for port– ...
Page 13
... L X FFF I/O Left I/O Right 0-7/8 0-7 CY7C138 CY7C139 Right Port INT R 0- FFE FFF Status Semaphore free Left port obtains semaphore Right side is denied access Right port is granted access to semaphore No change. Left port is denied access Left port obtains semaphore ...
Page 14
... TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 30.0 25.0 20.0 15.0 10.0 V =4.5V CC 5.0 T =25° 5.0 0 200 400 600 800 CAPACITANCE (pF) 14 CY7C138 CY7C139 OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 200 160 120 V =5. =25° 125 0 1.0 2.0 3.0 OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT vs ...
Page 15
... Ordering Information 4K x8 Dual-Port SRAM Speed Package (ns) Ordering Code 15 CY7C138–15JC 25 CY7C138–25JC CY7C138–25JI 35 CY7C138–35JC CY7C138–35JI 55 CY7C138–55JC CY7C138–55JI 4K x9 Dual-Port SRAM Speed Package (ns) Ordering Code 15 CY7C139–15JC 25 CY7C139–25JC CY7C139–25JI 35 CY7C139–35JC CY7C139–35JI 55 CY7C139–55JC CY7C139– ...