ad7868bq Analog Devices, Inc., ad7868bq Datasheet - Page 2

• Manufacturer Part Number: ad7868bq
• Description: Lc2mos Complete, 12-bit Analog I/o System
• Manufacturer: Analog Devices, Inc.

AD7868–SPECIFICATIONS
Parameter
DYNAMIC PERFORMANCE
DC ACCURACY
ANALOG INPUT
REFERENCE OUTPUT
LOGIC INPUTS (CONVST, CLK, CONTROL)
LOGIC OUTPUTS
CONVERSION TIME
POWER REQUIREMENTS
NOTES
1
2
3
4
5
6
7
8
Specifications subject to change without notice.
ADC SECTION
Temperature ranges are as follows: A/B Versions, –40 C to +85 C; T Version, –55 C to +125 C.
V
SNR calculation includes distortion and noise components.
SNR degradation due to asynchronous DAC updating during conversion is 0.1 dB typ.
Measured with respect to internal reference.
For capacitive loads greater than 50 pF a series resistor is required (see INTERNAL REFERENCE section).
Tying the CONTROL input to V
Sample tested @ +25 C to ensure compliance.
Signal-to-Noise Ratio
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise
Intermodulation Distortion (IMD)
Track/Hold Acquisition Time
Resolution
Minimum Resolution
Integral Nonlinearity
Integral Nonlinearity
Differential Nonlinearity
Bipolar Zero Error
Positive Gain Error
Negative Gain Error
Input Voltage Range
Input Current
RO ADC @ +25 C
RO ADC TC
RO ADC TC
Reference Load Sensitivity ( RO ADC vs. I)
Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Current
Input Capacitance, C
DR, RFS Outputs
RCLK Output
DR, RFS, RCLK Outputs
External Clock
Internal Clock
V
V
I
I
Total Power Dissipation
IN
DD
SS
DD
SS
T
Second Order Terms
Third Order Terms
Output Low Voltage, V
Output Low Voltage, V
Floating-State Leakage Current
Floating-State Output Capacitance
= 3 V
MIN
to T
MAX
7
(CONTROL Input Only)
IN
5
5
3, 4
IN
INL
INH
(V
6
8
unless otherwise noted.)
(SNR) @ +25 C
DD
OL
OL
= +5 V
2
DD
places the device in a factory test mode where normal operation is not exhibited.
8
5%, V
SS
= –5 V
A
Version
70
70
–78
–78
–78
–80
2
12
12
2.99/3.01 2.99/3.01 2.99/3.01 V min/V max
–1.5
2.4
0.8
10
0.4
0.4
15
10
10
+5
–5
22
12
170
12
0.9
5
5
5
3
1
25
10
10
10
1
5%, AGND = DGND = 0 V, f
B
Version
72
71
–78
–78
–78
–80
2
12
12
–1.5
2.4
0.8
10
0.4
0.4
15
10
10
+5
–5
22
12
170
12
1
0.9
5
5
5
3
1
25
40
10
10
10
1
T
Version
70
70
–76
–76
–76
–78
2
12
12
–1.5
2.4
0.8
10
0.4
0.4
15
10
10
+5
–5
25
13
190
–2–
12
1
0.9
5
5
5
3
1
25
50
10
10
10
1
Units
dB min
dB max
dB max
dB max
dB max
Bits
Bits
LSB typ
LSB max
LSB max
ppm/ C typ
mV max
V min
V max
pF max
V max
V max
pF max
mA max
mA max
mW max
dB min
LSB max
LSB max
LSB max
Volts
mA max
ppm/ C max
V nom
V nom
s max
A max
A max
A max
s max
s max
CLK
= 2.0 MHz external. All specifications T
Test Conditions/Comments
V
Typically 71.5 dB for 0 < V
V
Typically 71.5 dB for 0 < V
V
Typically 71.5 dB for 0 < V
fa = 9 kHz, fb = 9.5 kHz, f
fa = 9 kHz, fb = 9.5 kHz, f
No Missing Codes Are Guaranteed
Reference Load Current Change (0 A–500 A),
Reference Load Should Not Be Changed
During Conversion
V
V
V
V
I
I
The Internal Clock Has a Nominal Value of 2.0 MHz
For Both DAC and ADC
Cumulative Current from the Two V
Cumulative Current from the Two V
Typically 130 mW
SINK
SINK
5% for Specified Performance
5% for Specified Performance
IN
IN
IN
DD
DD
IN
IN
= 10 kHz Sine Wave, f
= 10 kHz Sine Wave, f
= 10 kHz Sine Wave, f
= 0 V to V
= V
= 5 V
= 5 V
= 1.6 mA, Pull-Up Resistor = 4.7 k
= 2.6 mA, Pull-Up Resistor = 2 k
SS
to DGND
5%
5%
DD
SAMPLE
SAMPLE
SAMPLE
SAMPLE
SAMPLE
IN
IN
IN
< 41.5 kHz
< 41.5 kHz
< 41.5 kHz
= 83 kHz
= 83 kHz
= 83 kHz
= 50 kHz
= 50 kHz
MIN
DD
SS
to T
Pins
Pins
MAX-
REV. B