ad7886kp Analog Devices, Inc., ad7886kp Datasheet - Page 13

• Manufacturer Part Number: ad7886kp
• Description: Lc2mos 12-bit, 750 Khz/1 Mhz, Sampling Adc
• Manufacturer: Analog Devices, Inc.

POWER SUPPLY CONNECTIONS
The PC board requires two analog power supplies and one 5 V
digital supply. Connections to the analog supply are made di-
rectly to the PC board as shown on the silkscreen in Figure 24.
The connections are labeled V+ and V–, and the range for both
of these supplies is 12 V to 15 V. Connection to the 5 V digital
supply is made through either of the two connectors (SKT3 or
SKT4). The +5 V analog supplies required by the AD7886 are
generated from voltage regulators on the V– and V+ power
supplies.
LINK OPTIONS
There are five link options, labeled LK1 to LK5, which must be
set before using the board.
LK1 Input Range Select
The AD7886 can accommodate three possible analog input
ranges: 0 V to 5 V, 0 to 10 V and +5 V. The link options are as
follows:
LK2 and LK3 Control Input Options
The evaluation board includes two latches to increase the data
access time when interfacing to the faster DSP machines. If
REV. B
CONNECTOR
0 V to 5 V
0 V to 10 V
A32/B32/
5 V
96-WAY
SKT3
C32
B18
B20
C14
A31
B11
C22
B27
C13
C12
C11
B6
A9
CONVST
+
DMD15
EDMACK
RD
DMD8
ECE6 (OUT1)
OUT2
DMD7
DMD0
EIRQ0
CS
CONVST
DIGITAL
5V
GND
Use Link C
Use Link B
Use Link A
0.1 F
LK5
C20
+
5V
SKT1
LK2
74HC374
O/P
Q7
Q0
Q7
Q0
O/P
+
GND
5V
IC9
74HC374
C19
10 F
GND
V
IC8
CC
V
CLK
LK3
CC
0.1 F
D7
D4
D3
D2
D1
D0
+V
Figure 23. Data Acquisition Circuit Using the AD7886
C23
CLK
D0
D7
–V
IN
+
78L05
GND
5V
IC5
OUT
IN
79L05
GND
IC6
DB4
DB3
DB0
BUSY
CS
RD
CONVST
V
DB11
OUT
DD
AD7886
IC1
V
SS
C10/C18
+
C8
0.1 F
V
+
5V
DGND
AGND
AGND
0.1 F
DD
5REF
V
SUM
VIN2
VIN1
REF
V
SS
–13–
C7
10 F
0.1 F
–
C10
5V
these latches are not required, they may be removed and the
data digital paths shorted out, i.e., latch inputs Dx shorted to
outputs Qx using wire links in the latch sockets. When using the
latches, the AD7886 control inputs, CS and RD, must be tied
low via links 2 and 3. The latches are updated by the rising edge
of the BUSY signal at the end of every conversion. Data is then
read by asserting the latch output enable signals. The alternative
is to remove the latches and assert the ADC’s control inputs
from either of the connectors, SKT3 or SKT4, as outlined in
the data sheet.
LK4 Analog Input Option
LK4 connects the analog input to a component grid or to a
buffer amplifier that drives the ADC input.
LK5
Data format can be 16-bits parallel or two bytes for 8-bit pro-
cessors. There are two data enable controls for the 74HC374
latches, labeled OUT1 and OUT2. OUT1 enables the 8 MSBs
(IC8), and OUT2 enables the 4 LSBs (IC9). Link options are:
for 16-bit format, include LK5, for a two byte read format,
remove LK5.
Latches Included
Insert Link 2
Insert Link 3
0.1 F
C9/C17
10 F
C14
10 F
C11
+V
A
C
B
AD707
0.1 F
C13
10 F
C16
LK1
IC4
0.1 F
+
–
C4
–V
C15
10 F
+V
AD845
0.1 F
C3
10 F
IC2
C2
V
OUT
Latches Removed
Remove Link 2
Remove Link 3
AD586
–V
GND
–
+
IC3
+V
IN
C1
10 F
LK4
0.1 F
AD7886
C6
SKT2
ANALOG
INPUT
+V
C5
10 F