ad7531ln Intersil Corporation, ad7531ln Datasheet - Page 4

• Manufacturer Part Number: ad7531ln
• Description: 10-bit, 12-bit, Multiplying D/a Converters
• Manufacturer: Intersil Corporation

Pin Descriptions
Definition of Terms
Nonlinearity: Error contributed by deviation of the DAC
transfer function from a “best straight line” through the actual
plot of transfer function. Normally expressed as a percent-
age of full scale range or in (sub)multiples of 1 LSB.
Resolution: It is addressing the smallest distinct analog
output change that a D/A converter can produce. It is
commonly expressed as the number of converter bits. A
converter with resolution of n bits can resolve output changes
of 2
conversion. Resolution by no means implies linearity.
Settling Time: Time required for the output of a DAC to set-
tle to within specified error band around its final value (e.g.,
1
LOW to HIGH and HIGH to LOW.
Gain Error: The difference between actual and ideal analog
output values at full scale range, i.e., all digital inputs at
HIGH state. It is expressed as a percentage of full scale
range or in (sub)multiples of 1 LSB.
Feedthrough Error: Error caused by capacitive coupling
from V
Output Capacitance: Capacitance from I
terminals to ground.
Output Leakage Current: Current which appears on I
terminal when all digital inputs are LOW or on I
terminal when all digital inputs are HIGH.
Detailed Description
The AD7520, AD7530, AD7521 and AD7531 are monolithic,
multiplying D/A converters. A highly stable thin film R-2R
resistor ladder network and NMOS SPDT switches form the
basis of the converter circuit, CMOS level shifters permit low
power TTL/CMOS compatible operation. An external voltage
/
AD7520/30
2
LSB) for a given digital input change, i.e., all digital inputs
-N
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
-
-
REF
of the full-scale range, e.g., 2
to I
AD7521/31
OUT1
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
with all digital inputs LOW.
R
Bits 1(MSB) Most Significant Digital Data Bit.
PIN NAME
FEEDBACK
I
I
Bit 10
Bit 11
Bit 12
V
OUT1
OUT2
GND
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
V+
REF
AD7520, AD7530, AD7521, AD7531
-N
Current Out summing junction of the R2R ladder network.
Current Out virtual ground, return path for the R2R ladder network.
Digital Ground. Ground potential for digital side of D/A.
Digital Bit 2.
Digital Bit 3.
Digital Bit 4.
Digital Bit 5.
Digital Bit 6.
Digital Bit 7.
Digital Bit 8.
Digital Bit 9.
Digital Bit 10 (AD7521/31). Least Significant Digital Data Bit (AD7520/30).
Digital Bit 11 (AD7521/31).
Least Significant Digital Data Bit (AD7521/31).
Power Supply +5V to +15V.
Voltage Reference Input to set the output range. Supplies the R2R resistor ladder.
Feedback resistor used for the current to voltage conversion when using an external Op Amp.
V
REF
OUT1
for a unipolar
and I
OUT2
OUT1
OUT2
10-10
or current reference and an operational amplifier are all that
is required for most voltage output applications.
A simplified equivalent circuit of the DAC is shown in the
Functional Diagram. The NMOS SPDT switches steer the lad-
der leg currents between I
be held either at ground potential. This configuration main-
tains a constant current in each ladder leg independent of the
input code.
Converter errors are further reduced by using separate
metal interconnections between the major bits and the
outputs. Use of high threshold switches reduce offset (leak-
age) errors to a negligible level.
The level shifter circuits are comprised of three inverters with
positive feedback from the output of the second to the first, see
Figure 1. This configuration results in TTL/CMOS compatible
operation over the full military temperature range. With the lad-
der SPDT switches driven by the level shifter, each switch is
binarily weighted for an ON resistance proportional to the
respective ladder leg current. This assures a constant voltage
drop across each switch, creating equipotential terminations for
the 2R ladder resistors and highly accurate leg currents.
CMOS INPUT
DTL/TTL/
V+
DESCRIPTION
FIGURE 1. CMOS SWITCH
1 3
OUT1
2
and I
4
OUT2
5
buses which must
6
7
I
TO LADDER
OUT2
8
I
OUT1
9