ics9248-157 ETC-unknow, ics9248-157 Datasheet - Page 2

• Manufacturer Part Number: ics9248-157
• Description: Chip Solution Pentium Using 1621/1632m Style Chipsets
• Manufacturer: ETC-unknow

Pin Descriptions
Advance Information
General Description
The ICS9248-157 is the Main clock solution for Notebook designs using the Intel ALI1621/1632M style chipset. Along with
an SDRAM buffer such as the ICS9179-03, it provides all necessary clock signals for such a system.
Spread spectrum may be enabled by driving pin 26, SPREAD# active (Low) at power-on. Spread spectrum typically reduces
system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding.
The ICS9248-157 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process
and temperature variations.
Third party brands and names are the property of their respective owners.
ICS9248-157
Pin number
11, 10, 9, 6
7, 15, 21
12
13
14
16
17
18
19
20
22
23
24
25
26
27
28
1
2
3
4
5
8
PCICLK (4:1)
CPU_STOP#
SEL_CPUF#
CPUCLK0/F
Pin name
PCI-STOP#
PCICLK_E
PCICLK_F
SPREAD#
CPUCLK1
PCICLK0
VDDPCI
VDD48
48MHz
DIV4#
VDDA
GNDL
VDDR
REF0
VDDL
REF1
GND
PD#
FS1
FS2
FS3
FS0
X1
X2
Output
Output
Output
Output
Output
Output
Output
Output
Output
Type
Power
Power
Power
Power
0utput
Power
Power
Power
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Frequency select pin
3.3V, 14.318 MHz reference clock output.
14.318 MHz crystal input
14.318 MHz crystal output
Frequency select pin
3.3 V free running PCI clock output, will not be stopped by the PCI_STOP#
Active low input to select CPUCLK0/F (pin 23) either normal CPUCLK or Free
running (not stoppable through CPU_STOP#) clock.
3.3V PCI clock output
3.3 V PCI clock outputs, generating timing requirements
Ground for clock outputs
3.3 V power for the PCI clock outputs
Early PCICLK output, offset from other PCICLKs, stopped by PCI-STOP#
3.3 V power for 48 MHz clocks
Frequency select pin
Fixed 48MHz clock.
Active low input, enables the CPUCLK and the PCICLK to run at 1/4 of the regular
frequecies
Asynchronous active low input pin used to power down the device into a low power
state. The internal clocks are disabled and the VCO and the crystal are stopped. The
latency of the power down will not be greater than 3ms.
Asynchronous active low input pin used to stop the CPUCLK in active low state, all
other clocks will continue to run. The CPUCLK will have a "Turnon " latency of at
least 3 CPU clocks.
3.3 V power for the core
Synchronous active low input used to stop the PCICLK in active low state. It will not
effect PCICLK_F or any other outputs.
Ground for the CPU and Host clock outputs
2.5V CPU clock output; can be selected to be free running by driving
SEL_CPUF# low
2.5 V CPU and Host clock outputs
2.5 V power for the CPU and Host clock outputs
enable. Active high = spread spectrum clocking disable.
Frequency select pin
3.3V, 14.318 MHz reference clock output.
3.3 V power for the REFCLK and crystal clock outputs
power-on spread spectrum enable option. Active low = spread spectrum clocking
2
Description