ics9p935 Integrated Device Technology, ics9p935 Datasheet - Page 5

• Manufacturer Part Number: ics9p935
• Description: Ddr I/ddr Ii Phase Lock Loop Zero Delay Buffer
• Manufacturer: Integrated Device Technology

Notes:
1.
2.
3.
4.
IDT
T
Max clock frequency
Application Frequency
Range
Input clock duty cycle
CLK stabilization
Output enable time
Output disable time
Period jitter
Half-period jitter
Input slew rate
Output clock slew rate
Cycle-to-cycle period jitter
Dynamic Phase Offset
Phase error
Output to Output Skew
SSC modulation frequency
SSC clock input frequency deviation
Timing Requirements
Switching Characteristics
A
ICS9P935
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
TM
= 0 - 70°C Supply Voltage AVDD, VDD = 1.8 V +/- 0.1V (unless otherwise stated)
Refers to transition on noninverting output in PLL bypass mode.
While the pulse skew is almost constant over frequency, the duty cycle error increases at
higher frequencies. This is due to the formula: duty cycle=t
decreases as the frequency goes up.
Switching characteristics guaranteed for application frequency range.
Static phase offset shifted by design.
/ICS
PARAMETER
TM
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
PARAMETER
SYMBOL
freq
1
freq
T
d
STAB
tin
App
op
t
SYMBOL
(phase error)
t
t
t
SLr1(o)
t
t
jit(hper)
SLr1(i)
jit (per)
jit(cc+)
t
jit(cc-)
( )dyn
1.8V+0.1V @ 25°C
1.8V+0.1V @ 25°C
t
skew
t
dis
en
CONDITIONS
2
OE to any output
OE to any output
Input Clock
Output Enable (OE), (OS)
5
wH
/t
CONDITION
c
, were the cycle (t
MIN
125
160
40
MAX
c
500
400
60
15
)
30.00
MIN
0.00
-40
-75
0.5
1.5
-50
-50
1
0
0
UNITS
MHz
MHz
µs
%
ICS9P935
TYP
2.5
2.5
0
MAX
-0.50
-40
40
75
40
50
50
40
33
REV H 12/1/08
8
8
4
3
UNITS
v/ns
v/ns
v/ns
kHz
ns
ns
ps
ps
ps
ps
ps
ps
ps
%