ics9p935 Integrated Device Technology, ics9p935 Datasheet - Page 7

• Manufacturer Part Number: ics9p935
• Description: Ddr I/ddr Ii Phase Lock Loop Zero Delay Buffer
• Manufacturer: Integrated Device Technology

Recommended Operating Condition (see note 1)
Notes:
1.
2.
3.
4.
IDT
T
Supply Voltage
Low level input voltage
High level input voltage
DC input signal voltage
(note 2)
Differential input signal
voltage (note 3)
Output differential cross-
voltage (note 4)
Input differential cross-
voltage (note 4)
High level output
current
Low level output current
Operating free-air
temperature
A
ICS9P935
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
TM
= 0 - 70°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
Unused inputs must be held high or low to prevent them from floating.
DC input signal voltage specifies the allowable DC execution of differential input.
Differential inputs signal voltages specifies the differential voltage [VTR-VCP] required
for switching, where VT is the true input level and VCP is the complementary input level.
Differential cross-point voltage is expected to track variations of V
at which the differential signal must be crossing.
/ICS
PARAMETER
TM
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
V
SYMBOL
DD
V
V
V
V
V
V
I
I
, A
T
OH
OL
OX
IH
IN
ID
IX
IL
A
VDD
DDRT,DDRC
DDRT,DDRC
DC - DDRT
AC - DDRT
CONDITIONS
7
DD
and is the voltage
V
V
V
DD
DD
DD
/2 + 0.18
/2 - 0.15
0.36
MIN
-0.3
/2 - 0.2
2.3
0.7
0
V
TYP
2.5
0.4
2.1
DD
/2
ICS9P935
V
V
V
V
V
DD
V
DD
DD
DD
DD
DD
/2 + 0.15
MAX
/2 - 0.18
/2 + 0.2
2.7
-30
-30
85
+ 0.3
+ 0.6
+ 0.6
REV H 12/1/08
UNITS
mA
mA
°C
V
V
V
V
V
V
V
V