ics650-12 Integrated Device Technology, ics650-12 Datasheet

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ics650-12

Manufacturer Part Number
ics650-12
Description
Mpeg Clock Synthesizer
Manufacturer
Integrated Device Technology
Datasheet
MPEG CLOCK SYNTHESIZER
Description
The ICS650-12 is a low cost, low-jitter, high-performance
clock synthesizer designed to produce fixed clock outputs of
13.5 MHz and 27.0 MHz, and four selectable clock outputs:
two Processor Clocks (PCLK1) and PCLK2), an Audio
Clock, and a Communications Clock (CCLK). Using analog
Phase-Locked Loop (PLL) techniques, the device uses a
27.0 MHz clock or fundamental crystal to produce clocks
ideal for Digital Video/MPEG-based applications.
Block Diagram
IDT™ / ICS™ MPEG CLOCK SYNTHESIZER
27.0 MHz crystal
or clock
PS2:0
AS2:0
CS1:0
Oscillator
Crystal
Buffer/
Input
1
Features
NOTE: EOL for non-green parts to occur on
and Control
Synthesis
Packaged in 20-pin tiny SSOP (QSOP)
Available in RoHS 5 (green) or RoHS 6 (green and lead
free) compliant package
Input frequency of 27.0 MHz
Zero ppm synthesis error in output clocks
Provides fixed 13.5 MHz and 27.0 MHz. Also provides
two selectable processor clocks, one audio clock, and
one communications clock.
Ideal for digital video MPEG-based applications
3.3 V or 5.0 V operating voltage
Entire chip powers down (when CS1=CS0=0)
5/13/10 per PDN U-09-01
Circuitry
Clock
/2
ICS650-12
DATASHEET
PCLK1
PCLK2
ACLK
CCLK
13.5 MHz
27.0 MHz
ICS650-12
REV D 102709

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ics650-12 Summary of contents

Page 1

... MPEG CLOCK SYNTHESIZER Description The ICS650- low cost, low-jitter, high-performance clock synthesizer designed to produce fixed clock outputs of 13.5 MHz and 27.0 MHz, and four selectable clock outputs: two Processor Clocks (PCLK1) and PCLK2), an Audio Clock, and a Communications Clock (CCLK). Using analog Phase-Locked Loop (PLL) techniques, the device uses a 27 ...

Page 2

... Entire chip powers-down (outputs stop low) when 40.00 CS1=CS0=0. 27.00 40.5 25.00 30.00 2 CLOCK SYNTHESIZER AS1 AS0 ACLK 0 0 12.288 0 1 11.2896 1 0 8.192 1 1 24.576 0 0 8.192 0 1 16.9344 1 0 18.432 1 1 11.2896 CS0 CCLK 0 All off* 1 20.00 0 66.6666 1 24.576 ICS650-12 REV D 102709 ...

Page 3

... Processor Clock Select Pin 0. See table on page 2. 20 PS1 Input Processor Clock Select Pin 1. See table on page 2. Key: Input = input with internal pull-up; XI and XO = crystal connections; Power = power supply connection; Output = output IDT™ / ICS™ MPEG CLOCK SYNTHESIZER Pin Description 3 CLOCK SYNTHESIZER ICS650-12 REV D 102709 ...

Page 4

... MPEG CLOCK SYNTHESIZER Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS650-12. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. ...

Page 5

... IDT™ / ICS™ MPEG CLOCK SYNTHESIZER Symbol Conditions All clocks t 0 2 VDD/2 VDD = 3.3 V VDD = 5.0 V VDD = 3.3 V, except CCLK = 20 MHz VDD = 5.0 V, except CCLK = 20 MHz 5 CLOCK SYNTHESIZER Min. Typ. Max. Units 27 MHz 0 1 ppm 1 100 ±300 ps ±200 ps ICS650-12 REV D 102709 ...

Page 6

... E1 3.80 4.00 0.150 e 0.635 Basic 0.025 Basic L 0.40 1.27 0.016 Package Temperature 20-pin SSOP 0 to +70 C 20-pin SSOP 0 to +70 C 20-pin SSOP 0 to +70 C 20-pin SSOP 0 to +70 C ICS650-12 Inches Max 0.069 0.010 0.012 0.010 0.344 0.244 0.157 0.050 8 c REV D 102709 ...

Page 7

... ICS650-12 MPEG CLOCK SYNTHESIZER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. www.idt.com © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc ...

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