is61lv12816l Integrated Silicon Solution, Inc., is61lv12816l Datasheet
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is61lv12816l
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is61lv12816l Summary of contents
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... Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS61LV12816L is packaged in the JEDEC standard 44-pin TSOP (Type II), 44-pin LQFP, and 48-pin mini BGA (6mm x 8mm). 128Kx16 ...
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... IS61LV12816L TRUTH TABLE Mode Not Selected X Output Disabled H X Read Write PIN CONFIGURATION 44-Pin TSOP (Type II) ( I/O0 7 I/O1 8 I/ GND 12 I/O4 13 I/O5 14 I/ A16 18 A15 19 A14 20 A13 21 A12 ...
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... IS61LV12816L PIN CONFIGURATION 48-Pin mini BGA ( I I/O I GND I/O NC A16 I/O A14 I/O A15 I/O NC A12 A13 A10 H A9 PIN DESCRIPTIONS A0-A16 Address Inputs I/O0-I/O15 Data Inputs/Outputs CE Chip Enable Input ...
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... IS61LV12816L ABSOLUTE MAXIMUM RATINGS Symbol Parameter V Power Supply Voltage Relative to GND DD V Terminal Voltage with Respect to GND TERM T Storage Temperature STG P Power Dissipation T Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied ...
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... IS61LV12816L POWER SUPPLY CHARACTERISTICS Symbol Parameter Test Conditions = Max Operating Supply Current mA Max. OUT I TTL Standby V = Max Current (TTL Inputs max IH I CMOS Standby V = Max Current – 0.2V, DD (CMOS Inputs) ...
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... IS61LV12816L AC TEST CONDITIONS Parameter Input Pulse Level 0V to 3.0V Input Rise and Fall Times Input and Output Timing and Reference Level Output Load See Figures 1 and 2 AC TEST LOADS OUTPUT Figure 1. READ CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Read Cycle Time RC t Address Access Time ...
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... IS61LV12816L AC WAVEFORMS (1,2) (Address Controlled) ( READ CYCLE NO. 1 ADDRESS D OUT PREVIOUS DATA VALID READ CYCLE NO. 2 (1,3) ADDRESS LZCE LB LZB HIGH-Z D OUT Notes HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB Address is valid prior to or coincident with CE LOW transition. ...
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... IS61LV12816L WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Write Cycle Time Write End t SCE t Address Setup Time AW to Write End t Address Hold from Write End HA t Address Setup Time SA LB, UB Valid to End of Write t PBW WE Pulse Width (OE = HIGH PWE WE Pulse Width (OE = LOW) ...
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... IS61LV12816L (1,2) (CE Controlled HIGH or LOW) WRITE CYCLE NO. 1 ADDRESS UB DATA UNDEFINED OUT D IN Integrated Silicon Solution, Inc. — www.issi.com — Rev. F 10/27/ VALID ADDRESS t SCE PWE1 t PWE2 t PBW t HZWE HIGH DATA IN VALID 1-800-379-4774 ISSI ® LZWE HD UB_CEWR1 ...
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... IS61LV12816L (1) (WE Controlled HIGH during Write Cycle) WRITE CYCLE NO. 2 ADDRESS OE CE LOW UB DATA UNDEFINED OUT D IN (WE Controlled LOW During Write Cycle) WRITE CYCLE NO. 3 ADDRESS OE LOW CE LOW UB DATA UNDEFINED OUT VALID ADDRESS ...
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... IS61LV12816L (LB, UB Controlled, Back-to-Back Write) WRITE CYCLE NO. 4 ADDRESS OE CE LOW WE UB HZWE D OUT DATA UNDEFINED D IN Notes: 1. The internal Write time is defined by the overlap LOW, UB and/ LOW, and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The t referenced to the rising or falling edge of the signal that terminates the Write ...
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... IS61LV12816L DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter V V for Data Retention Data Retention Current DR t Data Retention Setup Time SDR t Recovery Time RDR Note 1: Typical values are measured 3.3V DATA RETENTION WAVEFORM GND 12 Test Condition Options See Data Retention Waveform = 2 ...
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... IS61LV12816L-10T IS61LV12816L-10TL Industrial Range: –40°C to +85°C Speed (ns) Order Part No. 8 IS61LV12816L-8BI IS61LV12816L-8TI 10 IS61LV12816L-10BI IS61LV12816L-10BLI IS61LV12816L-10LQI IS61LV12816L-10LQLI IS61LV12816L-10TI IS61LV12816L-10TLI Integrated Silicon Solution, Inc. — www.issi.com — Rev. F 10/27/05 Package Plastic TSOP (Type II) Plastic TSOP (Type II), Lead-free Plastic TSOP (Type II) Plastic TSOP (Type II), Lead-free ...
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... Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — ...
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... Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — ...
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... Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — ...