mpc961p Integrated Device Technology, mpc961p Datasheet - Page 5

• Manufacturer Part Number: mpc961p
• Description: Lvpecl-input Lvcmos-ouput 200-mhz Low Voltage Clock Zero Delay Buffer
• Manufacturer: Integrated Device Technology

IDT™ Low Voltage Zero Delay Buffer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC961P
Low Voltage Zero Delay Buffer
MPC961P
Power Supply Filtering
it exhibits some sensitivities that would not necessarily be seen
on a fully digital product. Analog circuitry is naturally susceptible
to random noise, especially if this noise is seen on the power
supply pins. The MPC961P provides separate power supplies
for the output buffers (V
of the device. The purpose of this design technique is to isolate
the high switching noise digital outputs from the relatively
sensitive internal analog phase-locked loop. In a controlled
environment such as an evaluation board this level of isolation
is sufficient. However, in a digital system environment where it
is more difficult to minimize noise on the power supplies, a
second level of isolation may be required. The simplest form of
isolation is a power supply filter on the V
MPC961P.
MPC961P is most susceptible to noise with spectral content in
the 10 kHz to 5 MHz range. Therefore the filter should be
designed to target this range. The key parameter that needs to
be met in the final filter design is the DC voltage drop that will
be seen between the V
MPC961P. From the data sheet the I
sourced through the V
(5 mA maximum), assuming that a minimum of 2.375 V (V
3.3 V or V
resistor R
(V
drop criteria. The RC filter pictured will provide a broadband
filter with approximately 100:1 attenuation for noise whose
spectral content is above 20 kHz. As the noise frequency
crosses the series resonant point of an individual capacitor it's
overall impedance begins to look inductive and thus increases
with increasing frequency. The parallel capacitor combination
shown ensures that a low impedance path to ground exists for
frequencies well above the bandwidth of the PLL.
minimize the susceptibility to power supply noise (isolated
power and grounds and fully differential PLL) there still may be
applications in which overall performance is being degraded
due to system power supply noise. The power supply filter
496
CC
The MPC961P is a mixed analog/digital product and as such
Figure 3
Although the MPC961P has several design features to
= 3.3 V) or 5 to 15 Ω (V
V
CC
F
CC
shown in
illustrates a typical power supply filter scheme. The
= 2.5 V) must be maintained on the V
Figure 3. Power Supply Filter
R
R
F
F
Figure 3
R
= 270 Ω for V
= 5–15 Ω for V
CCA
F
CC
CC
C
) and the phase-locked loop (V
supply and the V
pin) is typically 2 mA
F
CC
must have a resistance of 270 Ω
33...100 nF
CC
= 2.5 V) to meet the voltage
CC
10 nF
= 3.3 V
= 2.5 V
CCA
CCA
current (the current
CCA
V
V
pin for the
CCA
CC
APPLICATIONS INFORMATION
pin of the
MPC961P
CCA
pin. The
CCA
CC
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
=
)
5
schemes discussed in this section should be adequate to
eliminate power supply noise related problems in most designs.
Driving Transmission Lines
signals in a terminated transmission line environment. To
provide the optimum flexibility to the user the output drivers
were designed to exhibit the lowest impedance possible. With
an output impedance of less than 15 Ω the drivers can drive
either parallel or series terminated transmission lines. For more
information on transmission lines the reader is referred to
application note AN1091.
distribution of signals is the method of choice. In a point-to-point
scheme either series terminated or parallel terminated
transmission lines can be used. The parallel technique
terminates the signal at the end of the line with a 50 Ω
resistance to V
DC current and thus only a single terminated line can be driven
by each output of the MPC961P clock driver. For the series
terminated case however there is no DC current draw, thus the
outputs can drive multiple series terminated lines.
illustrates an output driving a single series terminated line vs
two series terminated lines in parallel. When taken to its
extreme the fanout of the MPC961P clock driver is effectively
doubled due to its capability to drive multiple lines.
of an output driving a single line vs two lines. In both cases the
drive capability of the MPC961P output buffer is more than
sufficient to drive 50 Ω transmission lines on the incident edge.
Note from the delay measurements in the simulations a delta of
only 43 ps exists between the two differently loaded outputs.
This suggests that the dual line driving need not be used
exclusively to maintain the tight output-to-output skew of the
MPC961P. The output waveform in
waveform, this step is caused by the impedance mismatch seen
The MPC961P clock driver was designed to drive high speed
In most high performance clock networks point-to-point
The waveform plots of
IN
IN
Figure 4. Single versus Dual Transmission Lines
OUTPUT
OUTPUT
MPC961
BUFFER
MPC961
BUFFER
14 Ω
14 Ω
CC/
2. This technique draws a fairly high level of
R
R
R
Figure 5
S
S
S
= 36 Ω
= 36 Ω
= 36 Ω
show the simulation results
Figure 5
Z
Z
Z
O
O
O
= 50 Ω
= 50 Ω
= 50 Ω
shows a step in the
Figure 4
OutA
OutB0
OutB1
NETCOM
MPC961P