mpc9351 Integrated Device Technology, mpc9351 Datasheet - Page 10

• Manufacturer Part Number: mpc9351
• Description: Low Voltage Pll Clock Driver
• Manufacturer: Integrated Device Technology

IDT™ Low Voltage PLL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9351
Low Voltage PLL Clock Driver
10
MPC9351
PCLK
PCLK
Ext_FB
Figure 13. Propagation Delay (t
The deviation in t
in a random sample of cycles.
The variation in cycle time of a signal between adjacent cycles,
over a random sample of adjacent cycle pairs.
The time from the PLL controlled edge to the non-controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage.
TCLK
(CLK)
Ext_FB
Figure 15. Output Duty Cycle (DC)
Figure 17. Cycle-to-Cycle Jitter
0
for a controlled edge with respect to a t
t
T
P
Figure 19. I/O Jitter
N
t
(∅)
Test Reference
T
T
0
N+1
DC = t
V
CMR
P
T
/T
PD
JIT(∅)
0
T
x 100%
JIT(CC)
, static phase offset)
= |T
= |T
0
–T
N
1
–T
mean|
N+1
V
V
GND
CC
CC
V
V
GND
V
|
0
CMR
CC
CC
÷ 2
mean
÷ 2
10
TCLK
Ext_FB
The deviation in cycle time of a signal with respect to the ideal
period over a random sample of cycle.s
Figure 14. Propagation Delay (t
The pin-to-pin skew is defined as the worst case difference
in propagation delay between any similar delay path within a
single device.
t
F
Figure 20. Transition Time Test Reference
Figure 16. Output-to-Output Skew t
T
0
Figure 18. Period Jitter
t
(∅)
Advanced Clock Drivers Devices
t
SK(O)
Freescale Semiconductor
T
t
R
JIT(PER)
V
PD
CC
) Test Reference
0.55
= 3.3 V
2.4
= |T
N
–1/f
SK(O)
V
0
|
CC
V
V
GND
V
V
GND
V
V
GND
V
V
GND
CC
CC
CC
CC
1.8 V
0.6 V
= 2.5 V
CC
CC
CC
CC
÷ 2
÷ 2
÷ 2
÷ 2
NETCOM
MPC9351