mpc9351 Integrated Device Technology, mpc9351 Datasheet - Page 8

• Manufacturer Part Number: mpc9351
• Description: Low Voltage Pll Clock Driver
• Manufacturer: Integrated Device Technology

IDT™ Low Voltage PLL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9351
Low Voltage PLL Clock Driver
8
designed to target this range. The key parameter that needs
to be met in the final filter design is the DC voltage drop
across the series filter resistor (R
I
typically 3 mA (5 mA maximum), assuming that a minimum of
2.325 V (V
the V
resistance of 270 Ω (V
meet the voltage drop criteria.
defined by the required filter characteristics. The RC filter
should provide an attenuation greater than 40 dB for noise
whose spectral content is above 100 kHz. In the example RC
filter shown in
3–5 kHz, and the noise attenuation at 100 kHz is better than
42 dB.
of an individual capacitor, its overall impedance begins to
look inductive, and thus, increases with increasing frequency.
The parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL. Although the MPC9351 has
several design features to minimize the susceptibility to
power supply noise (isolated power and grounds and fully
differential PLL), there still may be applications in which
overall performance is being degraded due to system power
supply noise. The power supply filter schemes discussed in
this section should be adequate to eliminate power supply
noise related problems in most designs.
Driving Transmission Lines
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user, the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20 Ω, the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to Freescale application note
AN1091. In most high performance clock networks,
point-to-point distribution of signals is the method of choice.
In a point-to-point scheme, either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50 Ω resistance to V
thus only a single terminated line can be driven by each
output of the MPC9351 clock driver. For the series terminated
MPC9351
CCA
The minimum values for R
As the noise frequency crosses the series resonant point
The MPC9351 clock driver was designed to drive high-
This technique draws a fairly high level of DC current and
R
R
current (the current sourced through the V
CCA
F
F
= 270 Ω for V
= 9–10 Ω for V
V
CC
pin. The resistor R
CC
Figure 7. V
= 3.3 V or V
Figure
CC
CC
= 3.3 V
CC
= 2.5 V
R
7, the filter cut-off frequency is around
CC
F
CCA
÷ 2.
= 3.3 V) or 9–10 Ω (V
CC
C
F
F
Power Supply Filter
= 2.5 V) must be maintained on
F
shown in
33...100 nF
and the filter capacitor C
F
). From the data sheet, the
10 nF
C
C
F
F
= 1 µF for V
= 22 µF for V
Figure 7
V
V
CC
CC
CCA
CC
CCA
CC
must have a
= 3.3 V
= 2.5 V) to
MPC9351
= 2.5 V
pin) is
F
are
8
case, however, there is no DC current draw, thus the outputs
can drive multiple series terminated lines.
an output driving a single series terminated line versus two
series terminated lines in parallel. When taken to its extreme,
the fanout of the MPC9351 clock driver is effectively doubled
due to its capability to drive multiple lines.
results of an output driving a single line versus two lines. In
both cases, the drive capability of the MPC9351 output buffer
is more than sufficient to drive 50 Ω transmission lines on the
incident edge. Note from the delay measurements in the
simulations, a delta of only 43 ps exists between the two
differently loaded outputs. This suggests that dual line driving
need not be used exclusively to maintain the tight
output-to-output skew of the MPC9351. The output waveform
in
by the impedance mismatch seen looking into the driver. The
parallel combination of the 36 Ω series resistor plus the
output impedance does not match the parallel combination of
the line impedances. The voltage wave launched down the
two lines will equal:
unity reflection coefficient, to 2.6 V. It will then increment
towards the quiescent 3.0 V in steps separated by one round
trip delay (in this case 4.0 ns).
Figure 9
At the load end, the voltage will double, due to the near
The waveform plots in
IN
IN
Figure 8. Single versus Dual Transmission Lines
shows a step in the waveform. This step is caused
MPC9351
MPC9351
Output
Output
Buffer
Buffer
14Ω
14Ω
V
Z
R
R
V
L
0
L
S
0
= V
= 50 Ω || 50 Ω
= 36 Ω || 36 Ω
= 14 Ω
= 3.0 (25 ÷ (18 + 17 + 25)
= 1.31 V
S
(Z
R
R
R
Figure 9
0
S
S
S
Advanced Clock Drivers Devices
÷ (R
= 36Ω
= 36Ω
= 36Ω
S
+ R
Freescale Semiconductor
show the simulation
0
Z
Z
Z
O
O
O
+ Z
= 50Ω
= 50Ω
= 50Ω
Figure 8
0
))
illustrates
OutA
OutB0
OutB1
NETCOM
MPC9351