mpc9331 Integrated Device Technology, mpc9331 Datasheet - Page 3

• Manufacturer Part Number: mpc9331
• Description: 3.3v 1 6 Lvcmos Pll Clock Generator
• Manufacturer: Integrated Device Technology

IDT™ 3.3 V 1:6 LVCMOS PLL Clock Generator
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9331
3.3 V 1:6 LVCMOS PLL Clock Generator
Advanced Clock Drivers Devices
Freescale Semiconductor
Table 1. Pin Configuration
Table 2. Function Table
CCLK
PCLK, PCLK
FB_IN
FB_SEL
REF_SEL
PWR_DN
FSELA
FSELB
FSELC
PLL_EN
CLK_STOP0-1
OE/MR
QA0-1, QB0-1, QC0-1 Output
GND
V
V
REF_SEL
FB_SEL
PLL_EN
PWR_DN
FSELA
FSELB
FSELC
OE/MR
CLK_STOP[0:1]
CC_PLL
CC
Control
Pin
PWR_DN, FSELA, FSELB and FSELC control the operating PLL frequency range and input/output frequency ratios.
0
1
1
1
0
0
0
1
11
See
Default
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Supply
Supply
Supply
Table 8
I/O
LVCMOS
LVPECL
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Ground
V
V
through
PCLK is the PLL reference clock
Internal PLL feedback of 8. f
Test mode with PLL disabled. The reference clock is substituted
for the internal VCO output. MPC9331 is fully static and no
minimum frequency limit applies. All PLL related AC
characteristics are not applicable.
VCO ÷ 1 (High output frequency range)
Output divider ÷ 2
Output divider ÷ 2
Output divider ÷ 4
Outputs disabled (high-impedance state) and reset of the
device. During reset in external feedback configuration, the PLL
feedback loop is open. The VCO is tied to its lowest frequency.
The MPC9331 requires reset after any loss of PLL lock. Loss of
PLL lock may occur when the external feedback path is
interrupted. The length of the reset pulse should be greater than
one reference clock cycle (CCLK or PCLK). Reset does not
affect PLL lock in internal feedback configuration.
See
CC
CC
Type
Table 3
Table 10
PLL reference clock signal
Differential PECL reference clock signal
PLL feedback signal input, connect to an output
Feedback select
Reference clock select
Output frequency and power down select
Frequency divider select for bank A outputs
Frequency divider select for bank B outputs
Frequency divider select for bank C outputs
PLL enable/disable
Clock output enable/disable
Output enable/disable (high-impedance tristate) and device reset
Clock outputs
Negative power supply (GND)
PLL positive power supply (analog power supply). It is recommended to use external RC filter for
the analog power supply pin V
Positive power supply for I/O and core. All V
supply for correct operation
for supported frequency ranges and output to input frequency ratios.
VCO
0
= 8 * f
3
ref
CC_PLL.
Please see applications section for details.
Function
CC
pins must be connected to the positive power
CCLK is the PLL reference clock
External feedback. Zero-delay operation
enabled for CCLK or PCLK as reference
clock
Normal operation mode with PLL enabled.
VCO ÷ 2 (Low output frequency range)
Output divider ÷ 4
Output divider ÷ 4
Output divider ÷ 6
Outputs enabled (active)
1
MPC9331
NETCOM
MPC9331
3