mpc9331 Integrated Device Technology, mpc9331 Datasheet - Page 5

• Manufacturer Part Number: mpc9331
• Description: 3.3v 1 6 Lvcmos Pll Clock Generator
• Manufacturer: Integrated Device Technology

IDT™ 3.3 V 1:6 LVCMOS PLL Clock Generator
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9331
3.3 V 1:6 LVCMOS PLL Clock Generator
Advanced Clock Drivers Devices
Freescale Semiconductor
Table 7. AC Characteristics (V
10. All outputs in ÷4 divider configuration.
11. –3 dB point of PLL transfer characteristics.
1. AC characteristics apply for parallel output termination of 50 Ω to V
2. In bypass mode, the MPC9331 divides the input reference clock.
3. The input frequency f
4. V
5. Calculation of reference duty cycle limits: DC
6. The MPC9331 will operate with input rise/fall times up to 3.0 ns, but the AC characteristics, specifically t
7. Data valid for f
8. Data valid for 16.67 MHz < f
9. Output duty cycle is DC = (0.5 ± 500 ps ⋅ f
Symbol
V
t
t
t
t
t
JIT(PER)
PW,MIN
PLZ, HZ
PZL, LZ
JIT(CC)
t
t
CMR
t
t
t
f
f
JIT(∅)
f
LOCK
and the input swing lies within the V
be guaranteed if t
V
R
sk(O)
R
VCO
MAX
t
DC
BW
REF
(∅)
, t
, t
CMR
PP
F
F
(4)
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
Input reference frequency
PLL mode, external feedback
PLL mode, internal feedback
Input reference frequency in PLL bypass mode
VCO lock frequency range
Output Frequency
Peak-to-peak input voltage
Common Mode Range
Input Reference Pulse Width
CCLK Input Rise/Fall Time
Propagation Delay
(static phase offset)
Output-to-output Skew
Output duty cycle
Output Rise/Fall Time
Output Disable Time
Output Enable Time
Cycle-to-cycle jitter
Period Jitter
I/O Phase Jitter
PLL closed loop bandwidth
PLL mode, external feedback
Maximum PLL Lock Time
REF
R
= 50 MHz and a PLL feedback of ÷8 (e.g. QAx connected to FB_IN and FSELA=1, PWR_DN=1).
, t
F
REF
are within the specified range.
must match the VCO frequency range divided by the feedback divider ratio FB: f
(9)
REF
(10)
CC
Characteristics
< 100 MHz and any feedback divider. t
= 3.3V ± 5%, T
(3)
(6)
PP
(11)
(5)
(AC) specification. Violation of V
OUT
CCLK or PCLK to FB_IN
REF,MIN
) ⋅ 100%. (e.g. the DC range at f
A
CCLK to FB_IN
PCLK to FB_IN
= t
= 0°C to 70°C)
PW,MIN
(2)
(÷8 feedback)
÷12 feedback
÷12 feedback
PCLK, PCLK
PCLK, PCLK
÷ 4 feedback
÷ 6 feedback
÷ 8 feedback
÷2 feedback
÷4 feedback
÷6 feedback
÷8 feedback
÷12 output
RMS (1 σ)
÷2 output
÷4 output
÷6 output
÷8 output
⋅ f
REF
5
TT
(7)
(7)
(8)
⋅ 100% and DC
.
(1)
CMR
sk(O)
(T÷2)–500
100.0
16.67
100.0
16.67
–250
–180
or V
[s] = t
50.0
33.3
25.0
25.0
50.0
33.3
25.0
–3.0
Min
200
400
1.2
2.0
0.1
OUT
PP
sk(O)
= 100 MHz is 45% < DC < 55%).
impacts static phase offset t
REF,MAX
[°] ÷ (f
2.0–8.0
1.2–4.0
1.0–3.0
0.7–2.0
–130
Typ
–30
T÷2
REF
= 100% – DC
⋅ 360°).
(T÷2)+500
V
CC
240.0
120.0
240.0
120.0
(∅)
1000
+120
Max
80.0
60.0
40.0
60.0
80.0
60.0
40.0
+3.0
240
480
–50
150
200
125
1.0
1.0
8.0
10
25
10
REF
– 0.9
, t
REF,MIN
PW,MIN
= f
(∅)
VCO
.
.
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
, DC and f
Unit
mV
ms
ns
ns
ps
ps
ps
ps
ns
ns
ns
ps
ps
ps
V
°
÷ FB.
PLL locked
PLL locked
LVPECL
LVPECL
0.8 to 2.0 V
FB_SEL = 1
and PLL locked
0.55 to 2.4 V
Condition
MAX
CMR
MPC9331
can only
range
NETCOM
MPC9331
5