mpc9315far2 Integrated Device Technology, mpc9315far2 Datasheet

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mpc9315far2

Manufacturer Part Number
mpc9315far2
Description
2.5v And 3.3v Lvcmos Pll Clock Generator
Manufacturer
Integrated Device Technology
Datasheet

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IDT™ 2.5 V and 3.3 V CMOS PLL Clock Generator and Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
2.5 V and 3.3 V CMOS PLL Clock
Generator and Driver
Freescale Semiconductor
Technical Data
© Freescale Semiconductor, Inc., 2005. All rights reserved.
2.5 V and 3.3 V CMOS PLL Clock
Generator and Driver
designed for low-skew clock distribution in low-voltage mid-range to
high-performance telecom, networking and computing applications. The
MPC9315 offers 8 low-skew outputs and 2 selectable inputs for clock
redundancy. The outputs are configurable and support 1:1, 2:1, 4:1, 1:2 and 1:4
output to input frequency ratios. In addition, a selectable output 180° phase
control supports advanced clocking schemes with inverted clock signals. The
MPC9315 is specified for the extended temperature range of –40 to +85°C.
Features
Functional Description
requires a connection of one of the device outputs to the selected feedback (FB0 or FB1) input to close the PLL feedback path.
The reference clock frequency and the output divider for the feedback path determine the VCO frequency. Both must be selected
to match the VCO frequency range. With available output dividers of divide-by-1, divide-by-2 and divide-by-4, the internal VCO
of the MPC9315 is running at either 1x, 2x or 4x of the reference clock frequency. The frequency of the QA, QB, QC output groups
is either the equal, one half or one fourth of the selected VCO frequency and can be configured for each output bank using the
FSELA, FSELB and FSELC pins, respectively. The available output to input frequency ratios are 4:1, 2:1, 1:1, 1:2 and 1:4. The
REF_SEL pin selects one of the two available LVCMOS compatible reference input (CLK0 and CLK1) supporting clock redundant
applications. The selectable feedback input pin allows the user to select different feedback configurations and input to output
frequency ratios. The MPC9315 also provides a static test mode when the PLL supply pin (V
(GND). In test mode, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The test mode
is intended for system diagnostics, test and debug purposes. This test mode is fully static and the minimum clock frequency spec-
ification does not apply. The outputs can be disabled by deasserting the OE pin (logic high state). In PLL mode, deasserting OE
causes the PLL to lose lock due to no feedback signal presence at FB0 or FB1. Asserting OE will enable the outputs and close
the phase locked loop, also enabling the PLL to recover to normal operation. The MPC9315 is fully 2.5 V and 3.3 V compatible
and requires no external loop filter components. All inputs accept LVCMOS signals while the outputs provide LVCMOS compat-
ible levels with the capability to drive terminated 50 Ω transmission lines. For series terminated transmission lines, each of the
MPC9315 outputs can drive one or two traces giving the devices an effective fanout of 1:18. The device is packaged in a 7x7 mm
32-lead LQFP package.
zero propagation delay to multiple components on the board. In zero-delay buffer mode, the PLL minimizes phase offset between
the outputs and the reference signal.
The MPC9315 is a 2.5 V and 3.3 V compatible, PLL based clock generator
The MPC9315 utilizes PLL technology to frequency and phase lock its outputs onto an input reference clock. Normal operation
The fully integrated PLL of the MPC9315 allows the low skew outputs to lock onto a clock input and distribute it with essentially
Configurable 8 outputs LVCMOS PLL clock generator
Compatible to various microprocessors such as PowerQUICC I and II
Wide range output clock frequency of 18.75 to 160 MHz
2.5 V and 3.3 V CMOS compatible
Designed for mid-range to high-performance telecom, networking and
computer applications
Fully integrated PLL supports spread spectrum clocking
Two selectable LVCMOS clock inputs
32-Lead Pb-free package available
Supports applications requiring clock redundancy
Max. output skew of 120 ps (80 ps within one bank)
Selectable output configurations (1:1, 2:1, 4:1, 1:2, 1:4 frequency ratios)
External PLL feedback path and selectable feedback configuration
Tristable outputs
32-Lead LQFP package
Ambient operating temperature range of -40 to +85°C
1
CCA
32-LEAD LQFP PACKAGE
32-LEAD LQFP PACKAGE
CLOCK GENERATOR
2.5 V AND 3.3 V PLL
Pb-FREE PACKAGE
) is pulled to logic low state
MPC9315
LOW VOLTAGE
CASE 873A-04
CASE 873A-04
FA SUFFIX
AC SUFFIX
DATA SHEET
Rev. 4, 08/2005
MPC9315
MPC9315
MPC9315
2

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mpc9315far2 Summary of contents

Page 1

... In zero-delay buffer mode, the PLL minimizes phase offset between the outputs and the reference signal. IDT™ 2.5 V and 3.3 V CMOS PLL Clock Generator and Driver © Freescale Semiconductor, Inc., 2005. All rights reserved. Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc MPC9315 LOW VOLTAGE 2.5 V AND 3.3 V PLL ...

Page 2

... FSELC (PULLDOWN) OE GND QA1 QA0 V FSELC FSELB FSELA GND MPC9315 IDT™ 2.5 V and 3.3 V CMOS PLL Clock Generator and Driver Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc CCA CLK PLL Ref 1 CLK÷ – 160 MHz CLK÷ ...

Page 3

... Functional operation under absolute-maximum-rated conditions is not implied. IDT™ 2.5 V and 3.3 V CMOS PLL Clock Generator and Driver Advanced Clock Drivers Devices Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Freescale Semiconductor Type LVCMOS ...

Page 4

... The MPC9315 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission line to a termination voltage Inputs have pull-up or pull-down resistors affecting the input current. MPC9315 IDT™ 2.5 V and 3.3 V CMOS PLL Clock Generator and Driver Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 4 Min Typ ÷ 2 ...

Page 5

... V 2. Inputs have pull-up or pull-down resistors affecting the input current. IDT™ 2.5 V and 3.3 V CMOS PLL Clock Generator and Driver Advanced Clock Drivers Devices Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Freescale Semiconductor (1) = 3.3 V ± 5 -40° ...

Page 6

... CC 3. I/O jitter depends on VCO frequency. Please see application section for I/O jitter versus VCO frequency characteristics. MPC9315 IDT™ 2.5 V and 3.3 V CMOS PLL Clock Generator and Driver Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 6 (1) = 2.5 V ± 5 -40° to 85°C) ...

Page 7

... Output frequency relationship with respect to input reference frequency CLK. IDT™ 2.5 V and 3.3 V CMOS PLL Clock Generator and Driver Advanced Clock Drivers Devices Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Freescale Semiconductor APPLICATIONS INFORMATION ratios of the reference clock input to the outputs are 1:1, 1:2, ...

Page 8

... MHz QB outputs 37.50 MHz QC outputs 18.75 MHz Figure 5. MPC9315 180° Phase Inversion Configuration MPC9315 IDT™ 2.5 V and 3.3 V CMOS PLL Clock Generator and Driver Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 8 fref = 75 MHz 160 MHz 80 MHz 1 40 MHz 0 MPC9315 1:1 frequency configuration (feedback of QB3 = 75 MHz) ...

Page 9

... IDT™ 2.5 V and 3.3 V CMOS PLL Clock Generator and Driver Advanced Clock Drivers Devices Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Freescale Semiconductor The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. In the following example calculation, an I/O jitter confidence factor of 99.7% (± ...

Page 10

... MPC9315 IDT™ 2.5 V and 3.3 V CMOS PLL Clock Generator and Driver Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 10 As the noise frequency crosses the series resonant point of an individual capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency ...

Page 11

... Z = 50Ω IDT™ 2.5 V and 3.3 V CMOS PLL Clock Generator and Driver Advanced Clock Drivers Devices Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Freescale Semiconductor At the load end the voltage will double, due to the near unity reflection coefficient will then increment towards the quiescent 3 ...

Page 12

... Figure 20. I/O Jitter MPC9315 IDT™ 2.5 V and 3.3 V CMOS PLL Clock Generator and Driver Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 12 CLK0, 1 FB0 (∅) Figure 15. Propagation delay (t , SPO) Test Reference (∅ ...

Page 13

... MPC9315 2.5 V and 3.3 V CMOS PLL Clock Generator and Driver IDT™ 2.5 V and 3.3 V CMOS PLL Clock Generator and Driver Advanced Clock Drivers Devices Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Freescale Semiconductor PACKAGE DIMENSIONS CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE ...

Page 14

... MPC9315 2.5 V and 3.3 V CMOS PLL Clock Generator and Driver MPC9315 IDT™ 2.5 V and 3.3 V CMOS PLL Clock Generator and Driver Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 14 PACKAGE DIMENSIONS CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE 14 NETCOM PAGE MPC9315 ...

Page 15

... MPC9315 2.5 V and 3.3 V CMOS PLL Clock Generator and Driver IDT™ 2.5 V and 3.3 V CMOS PLL Clock Generator and Driver Advanced Clock Drivers Devices Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Freescale Semiconductor PACKAGE DIMENSIONS CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE ...

Page 16

... Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners ...

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