mpc9315far2 Integrated Device Technology, mpc9315far2 Datasheet - Page 5

no-image

mpc9315far2

Manufacturer Part Number
mpc9315far2
Description
2.5v And 3.3v Lvcmos Pll Clock Generator
Manufacturer
Integrated Device Technology
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC9315FAR2
0
IDT™ 2.5 V and 3.3 V CMOS PLL Clock Generator and Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9315
2.5 V and 3.3 V CMOS PLL Clock Generator and Driver
Advanced Clock Drivers Devices
Freescale Semiconductor
Table 6. AC Characteristics (V
Table 7. DC Characteristics (V
1. AC characteristics apply for parallel output termination of 50 Ω to V
2. The VCO range in ÷1 feedback configuration (e.g. QAx connected to FBx and FSELA = 0) is limited to 100 ≤ f
3. I/O jitter depends on VCO frequency. Please see application section for I/O jitter versus VCO frequency characteristics.
1. The MPC9315 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated
2. Inputs have pull-up or pull-down resistors affecting the input current.
Symbol
t
Symbol
t
t
t
JIT(PER)
PLZ, HZ
PZL, LZ
t
t
JIT(CC)
t
f
Z
f
f
SK(∅)
JIT(∅)
I
I
refDC
LOCK
V
t
t
BW
next revision of the MPC9315 for improved VCO frequency range.
V
transmission line to a termination voltage of V
VCO
MAX
t
DC
V
CCA
CCQ
V
f
r
r
OUT
I
(∅)
ref
, t
, t
OH
IN
OL
IH
IL
f
f
Input Frequency
VCO Lock Range
Maximum Output Frequency
Reference Input Duty Cycle
CLK0, CLK1 Input Rise/Fall Time
Propagation Delay
(Static Phase Offset)
Output-to-Output Skew
Output Duty Cycle
Output Rise/Fall Time
Output Disable Time
Output Enable Time
PLL closed loop bandwidth
Cycle-to-Cycle Jitter
Period Jitter
I/O Phase Jitter
Maximum PLL Lock Time
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Output Impedance
Input Current
Maximum PLL Supply Current
Maximum Quiescent Supply Current
(2)
Characteristics
Characteristics
CC
CC
= 3.3 V ± 5%, T
= 2.5 V ± 5%, T
CLK0 or CLK1 to FB
PLL bypass mode
Within one bank
÷1 feedback
÷2 feedback
÷4 feedback
÷1 feedback
÷2 feedback
÷4 feedback
Any output
TT
÷1 output
÷2 output
÷4 output
. Alternatively, the device drives up to two 50 Ω series terminated transmission lines.
(1σ)
(1σ)
(1σ)
A
A
= -40° to 85°C)
= -40° to 85°C)
100
37.50
18.75
37.50
18.75
75
-150
Min
Min
0.1
1.7
1.8
75
25
45
0
5
(2)
TT
(2)
.
(1)
8.0 - 25
0.6 - 6.0
2.0 - 20
17 - 20
TBD
Typ
Typ
8.0
2.0
50
10
(3)
V
CC
+150
±200
TBD
TBD
Max
Max
160
160
160
120
1.0
1.0
1.0
0.7
0.6
5.0
1.0
80
40
80
40
75
80
55
10
10
22
15
+ 0.3
VCO
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
Unit
mA
mA
ms
µA
ns
ps
ps
ps
ns
ns
ns
ps
ps
ps
%
%
≤ 160 MHz. Please see
V
V
V
V
PLL locked
PLL locked
PLL locked
V
0.8 to 2.0 V
PLL locked
0.55 to 2.4 V
RMS value
RMS value
RMS value
LVCMOS
LVCMOS
I
I
V
GND
V
All V
OH
OL
CCA
IN
CCA
Condition
Condition
= 15 mA
= –15 mA
= V
CC
MPC9315
= GND
Pin
CC
Pins
NETCOM
or
(1)
MPC9315
5

Related parts for mpc9315far2